Shanth Murthy 76062b4ae2 platform/x86: intel_pmc_ipc: read s0ix residency API ... This patch adds a new API to indicate S0ix residency in usec. It utilizes the PMC Global Control Registers (GCR) to read deep and shallow S0ix residency. PMC MMIO resources: o Lower 4kB: IPC1 (PMC inter-processor communication) interface o Upper 4kB: GCR (Global Control Registers) This enables the power management framework to take corrective actions when the platform fails to enter S0ix after kernel freeze as part of the suspend to idle flow. (echo freeze > /sys/power/state). This is expected to be used with a S0ix failsafe framework such as: <https://lwn.net/Articles/689505/> [rajneesh: folded in "fix division in 32-bit case" from Andy Shevchenko] Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by: Shanth Murthy <shanth.murthy@intel.com> [andy: fixed kbuild error, removed "total" from variables, fixed macro] Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>		2017-02-24 23:48:46 -08:00
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asm	platform/x86: intel_pmc_ipc: read s0ix residency API	2017-02-24 23:48:46 -08:00
uapi/asm	Small release, the most interesting stuff is x86 nested virt improvements.	2016-12-13 15:47:02 -08:00