Yixun Lan 75eccf5ed8 clk: meson: gxbb: fix wrong clock for SARADC/SANA ... According to the datasheet, in Meson-GXBB/GXL series, The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22], while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10]. Test passed at gxl-s905x-p212 board. The following published datasheets are wrong and should be updated [1] GXBB v1.1.4 [2] GXL v0.3_20170314 Fixes: 738f66d321 ("clk: gxbb: add AmLogic GXBB clk controller driver") Tested-by: Xingyu Chen <xingyu.chen@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>		2017-11-27 14:33:38 +01:00
..
clk-audio-divider.c	clk: meson: add audio clock divider support	2017-04-07 16:50:44 +02:00
clk-cpu.c	clk: meson8b: clean up cpu clocks	2016-06-22 18:02:35 -07:00
clk-mpll.c	clk: meson: mpll: fix mpll0 fractional part ignored	2017-08-01 14:18:31 +02:00
clk-pll.c	clk: meson: Add support for parameters for specific PLLs	2017-04-04 12:05:12 -07:00
clkc.h	clk: meson: mpll: fix mpll0 fractional part ignored	2017-08-01 14:18:31 +02:00
gxbb-aoclk-32k.c	clk: meson: gxbb-aoclk: Add CEC 32k clock	2017-08-04 18:02:02 +02:00
gxbb-aoclk-regmap.c	clk: meson: gxbb-aoclk: Switch to regmap for register access	2017-08-04 18:02:01 +02:00
gxbb-aoclk.c	clk: meson: gxbb-aoclk: Add CEC 32k clock	2017-08-04 18:02:02 +02:00
gxbb-aoclk.h	clk: meson: gxbb-aoclk: Add CEC 32k clock	2017-08-04 18:02:02 +02:00
gxbb.c	clk: meson: gxbb: fix wrong clock for SARADC/SANA	2017-11-27 14:33:38 +01:00
gxbb.h	clk: meson: gxbb: Add VPU and VAPB clockids	2017-10-20 10:24:30 +02:00
Kconfig	clk: meson: meson8b: register the built-in reset controller	2017-08-04 18:01:58 +02:00
Makefile	clk: meson: gxbb-aoclk: Add CEC 32k clock	2017-08-04 18:02:02 +02:00
meson8b.c	Amlogic clock driver updates for 4.14	2017-08-23 15:28:52 -07:00
meson8b.h	clk: meson: meson8b: register the built-in reset controller	2017-08-04 18:01:58 +02:00