forked from Minki/linux
ee4eff6ff6
On the Unisys ES7000/ONE system, we encountered a problem where performing a kexec reboot or dump on any cell other than cell 0 causes the system timer to stop working, resulting in a hang during timer calibration in the new kernel. We traced the problem to one line of code in disable_IO_APIC(), which needs to restore the timer's IO-APIC configuration before rebooting. The code is currently using the 4-bit physical destination field, rather than using the 8-bit logical destination field, and it cuts off the upper 4 bits of the timer's APIC ID. If we change this to use the logical destination field, the timer works and we can kexec on the upper cells. This was tested on two different cells (0 and 2) in an ES7000/ONE system. For reference, the relevant Intel xAPIC spec is kept at ftp://download.intel.com/design/chipsets/e8501/datashts/30962001.pdf, specifically on page 334. Signed-off-by: Benjamin M Romer <benjamin.romer@unisys.com> Signed-off-by: Andi Kleen <ak@suse.de> Cc: Andi Kleen <ak@suse.de> Cc: "Eric W. Biederman" <ebiederm@xmission.com> Cc: Vivek Goyal <vgoyal@in.ibm.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
130 lines
2.5 KiB
C
130 lines
2.5 KiB
C
#ifndef __ASM_IO_APIC_H
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#define __ASM_IO_APIC_H
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#include <asm/types.h>
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#include <asm/mpspec.h>
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/*
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* Intel IO-APIC support for SMP and UP systems.
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*
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* Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
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*/
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#define APIC_MISMATCH_DEBUG
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/*
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* The structure of the IO-APIC:
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*/
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union IO_APIC_reg_00 {
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u32 raw;
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struct {
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u32 __reserved_2 : 14,
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LTS : 1,
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delivery_type : 1,
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__reserved_1 : 8,
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ID : 8;
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} __attribute__ ((packed)) bits;
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};
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union IO_APIC_reg_01 {
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u32 raw;
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struct {
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u32 version : 8,
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__reserved_2 : 7,
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PRQ : 1,
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entries : 8,
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__reserved_1 : 8;
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} __attribute__ ((packed)) bits;
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};
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union IO_APIC_reg_02 {
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u32 raw;
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struct {
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u32 __reserved_2 : 24,
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arbitration : 4,
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__reserved_1 : 4;
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} __attribute__ ((packed)) bits;
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};
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union IO_APIC_reg_03 {
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u32 raw;
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struct {
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u32 boot_DT : 1,
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__reserved_1 : 31;
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} __attribute__ ((packed)) bits;
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};
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/*
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* # of IO-APICs and # of IRQ routing registers
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*/
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extern int nr_ioapics;
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extern int nr_ioapic_registers[MAX_IO_APICS];
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enum ioapic_irq_destination_types {
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dest_Fixed = 0,
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dest_LowestPrio = 1,
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dest_SMI = 2,
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dest__reserved_1 = 3,
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dest_NMI = 4,
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dest_INIT = 5,
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dest__reserved_2 = 6,
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dest_ExtINT = 7
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};
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struct IO_APIC_route_entry {
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__u32 vector : 8,
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delivery_mode : 3, /* 000: FIXED
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* 001: lowest prio
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* 111: ExtINT
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*/
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dest_mode : 1, /* 0: physical, 1: logical */
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delivery_status : 1,
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polarity : 1,
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irr : 1,
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trigger : 1, /* 0: edge, 1: level */
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mask : 1, /* 0: enabled, 1: disabled */
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__reserved_2 : 15;
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__u32 __reserved_3 : 24,
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dest : 8;
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} __attribute__ ((packed));
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/*
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* MP-BIOS irq configuration table structures:
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*/
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/* I/O APIC entries */
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extern struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
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/* # of MP IRQ source entries */
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extern int mp_irq_entries;
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/* MP IRQ source entries */
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extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
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/* non-0 if default (table-less) MP configuration */
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extern int mpc_default_type;
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/* 1 if "noapic" boot option passed */
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extern int skip_ioapic_setup;
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/*
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* If we use the IO-APIC for IRQ routing, disable automatic
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* assignment of PCI IRQ's.
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*/
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#define io_apic_assign_pci_irqs (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)
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#ifdef CONFIG_ACPI
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extern int io_apic_get_version (int ioapic);
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extern int io_apic_get_redir_entries (int ioapic);
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extern int io_apic_set_pci_routing (int ioapic, int pin, int irq, int, int);
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#endif
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extern int sis_apic_bug; /* dummy */
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void enable_NMI_through_LVT0 (void * dummy);
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extern spinlock_t i8259A_lock;
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#endif
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