5f03dc2002
This adds support for the Broadcom timer, used in the following SoCs: BCM11130, BCM11140, BCM11351, BCM28145, BCM28155 Updates from V6: - Split DT portion into a separate patch Updates from V5: - Rebase to latest arm-soc/for-next Updates from V4: - Switch code to use CLOCKSOURCE_OF_DECLARE Updates from V3: - Migrate to 3.9 timer framework updates Updates from V2: - prepend static fns + fields with kona_ Updates from V1: - Rename bcm_timer.c to bcm_kona_timer.c - Pull .h into bcm_kona_timer.c - Make timers static - Clean up comment block - Switched to using clockevents_config_and_register - Added an error to the get_timer loop if it repeats too much - Added to Documentation/devicetree/bindings/arm/bcm/bcm,kona-timer.txt - Added missing readl to timer_disable_and_clear Note: bcm,kona-timer was kept as the 'compatible' field to make it specific enough for when there are multiple bcm timers (bcm,timer is too generic). Signed-off-by: Christian Daudt <csd@broadcom.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: John Stultz <john.stultz@linaro.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
59 lines
1.4 KiB
Plaintext
59 lines
1.4 KiB
Plaintext
/*
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* Copyright (C) 2012 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/include/ "skeleton.dtsi"
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/ {
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model = "BCM11351 SoC";
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compatible = "bcm,bcm11351";
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interrupt-parent = <&gic>;
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chosen {
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bootargs = "console=ttyS0,115200n8";
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};
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gic: interrupt-controller@3ff00100 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x3ff01000 0x1000>,
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<0x3ff00100 0x100>;
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};
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uart@3e000000 {
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compatible = "bcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
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status = "disabled";
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reg = <0x3e000000 0x1000>;
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clock-frequency = <13000000>;
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interrupts = <0x0 67 0x4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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L2: l2-cache {
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compatible = "arm,pl310-cache";
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reg = <0x3ff20000 0x1000>;
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cache-unified;
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cache-level = <2>;
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};
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timer@35006000 {
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compatible = "bcm,kona-timer";
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reg = <0x35006000 0x1000>;
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interrupts = <0x0 7 0x4>;
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clock-frequency = <32768>;
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};
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};
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