linux/drivers/gpu/drm/amd/display/dc/dml/dcn20
Gabe Teeger e5fc78252c drm/amd/display: Add support for zstate during extended vblank
[why]
When we enter FREESYNC_STATE_VIDEO, we want to use the extra vblank
portion to enter zstate if possible.

[how]
When we enter freesync, a full update is triggered and the new vtotal
with extra lines is passed to dml in a stream update. The time gained
from extra vblank lines is calculated in microseconds. We allow zstate
entry if the time gained is greater than 5 ms, which is the current
policy. Furthermore, an optimized value for min_dst_y_next_start is
calculated and written to its register. When exiting freesync, another
full update is triggered and default values are restored.

Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Gabe Teeger <gabe.teeger@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-25 12:40:25 -04:00
..
dcn20_fpu.c drm/amd/display: Add support for zstate during extended vblank 2022-03-25 12:40:25 -04:00
dcn20_fpu.h drm/amd/display: move FPU operations from dcn21 to dml/dcn20 folder 2022-03-15 14:25:16 -04:00
display_mode_vba_20.c
display_mode_vba_20.h
display_mode_vba_20v2.c drm/amd/display: cleanup idents after a revert 2021-08-31 14:19:20 -04:00
display_mode_vba_20v2.h
display_rq_dlg_calc_20.c drm/amdgpu/display: Remove t_srx_delay_us. 2022-01-25 17:54:23 -05:00
display_rq_dlg_calc_20.h drm/amd/display: Pass display_pipe_params_st as const in DML 2021-09-23 15:17:29 -04:00
display_rq_dlg_calc_20v2.c drm/amdgpu/display: Remove t_srx_delay_us. 2022-01-25 17:54:23 -05:00
display_rq_dlg_calc_20v2.h drm/amd/display: Pass display_pipe_params_st as const in DML 2021-09-23 15:17:29 -04:00