4fcbe1f5b6
Configure the vuart in such a way that it does not inhibit the SuperIO's UART from functioning correctly. This allows the same DTS to be used for both configurations with SuperIO and VUART (depending on the BIOS build). The decision on whether to actually enable VUART can then be made at runtime. This change also enables the new uart_routing driver for the SuperIO case. Signed-off-by: Oskar Senft <osk@google.com> Link: https://lore.kernel.org/r/20211130184855.1779353-1-osk@google.com Signed-off-by: Joel Stanley <joel@jms.id.au>
529 lines
10 KiB
Plaintext
529 lines
10 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/dts-v1/;
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#include "aspeed-g5.dtsi"
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#include <dt-bindings/gpio/aspeed-gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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model = "Tyan S7106 BMC";
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compatible = "tyan,s7106-bmc", "aspeed,ast2500";
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chosen {
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stdout-path = &uart5;
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bootargs = "console=ttyS4,115200 earlycon";
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x20000000>;
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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p2a_memory: region@987f0000 {
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no-map;
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reg = <0x987f0000 0x00010000>; /* 64KB */
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};
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vga_memory: framebuffer@9f000000 {
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no-map;
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reg = <0x9f000000 0x01000000>; /* 16M */
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};
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gfx_memory: framebuffer {
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size = <0x01000000>; /* 16M */
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alignment = <0x01000000>;
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compatible = "shared-dma-pool";
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reusable;
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};
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};
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leds {
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compatible = "gpio-leds";
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identify {
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gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>;
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};
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heartbeat {
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gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>;
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};
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};
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iio-hwmon {
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compatible = "iio-hwmon";
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io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
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<&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
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<&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>,
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<&adc 12>, <&adc 13>, <&adc 14>;
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};
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iio-hwmon-battery {
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compatible = "iio-hwmon";
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io-channels = <&adc 15>;
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};
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};
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&fmc {
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status = "okay";
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flash@0 {
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label = "bmc";
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status = "okay";
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m25p,fast-read;
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#include "openbmc-flash-layout.dtsi"
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};
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};
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&spi1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi1_default>;
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flash@0 {
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status = "okay";
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label = "pnor";
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m25p,fast-read;
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};
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};
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&uart1 {
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/* Rear RS-232 connector */
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_txd1_default
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&pinctrl_rxd1_default>;
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};
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&uart2 {
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/* RS-232 connector on header */
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_txd2_default
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&pinctrl_rxd2_default>;
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};
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&uart3 {
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/* Alternative to vuart to internally connect (route) to uart1
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* when vuart cannot be used due to BIOS limitations.
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*/
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status = "okay";
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};
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&uart4 {
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/* Alternative to vuart to internally connect (route) to the
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* external port usually used by uart1 when vuart cannot be
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* used due to BIOS limitations.
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*/
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status = "okay";
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};
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&uart5 {
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/* BMC "debug" (console) UART; connected to RS-232 connector
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* on header; selectable via jumpers as alternative to uart2
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*/
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status = "okay";
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};
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&uart_routing {
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status = "okay";
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};
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&vuart {
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status = "okay";
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/* We enable the VUART here, but leave it in a state that does
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* not interfere with the SuperIO. The goal is to have both the
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* VUART and the SuperIO available and decide at runtime whether
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* the VUART should actually be used. For that reason, configure
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* an "invalid" IO address and an IRQ that is not used by the
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* BMC.
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*/
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aspeed,lpc-io-reg = <0xffff>;
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aspeed,lpc-interrupts = <15 IRQ_TYPE_LEVEL_HIGH>;
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};
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&lpc_ctrl {
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status = "okay";
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};
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&p2a {
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status = "okay";
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memory-region = <&p2a_memory>;
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};
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&lpc_snoop {
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status = "okay";
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snoop-ports = <0x80>;
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};
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&adc {
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status = "okay";
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};
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&vhub {
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status = "okay";
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};
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&pwm_tacho {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm0_default
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&pinctrl_pwm1_default
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&pinctrl_pwm3_default
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&pinctrl_pwm4_default>;
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/* CPU fan #0 */
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fan@0 {
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reg = <0x00>;
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aspeed,fan-tach-ch = /bits/ 8 <0x00>;
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};
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/* CPU fan #1 */
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fan@1 {
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reg = <0x01>;
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aspeed,fan-tach-ch = /bits/ 8 <0x01>;
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};
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/* PWM group for chassis fans #1, #2, #3 and #4 */
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fan@2 {
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reg = <0x03>;
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aspeed,fan-tach-ch = /bits/ 8 <0x02>;
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};
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fan@3 {
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reg = <0x03>;
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aspeed,fan-tach-ch = /bits/ 8 <0x03>;
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};
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fan@4 {
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reg = <0x03>;
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aspeed,fan-tach-ch = /bits/ 8 <0x04>;
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};
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fan@5 {
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reg = <0x03>;
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aspeed,fan-tach-ch = /bits/ 8 <0x05>;
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};
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/* PWM group for chassis fans #5 and #6 */
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fan@6 {
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reg = <0x04>;
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aspeed,fan-tach-ch = /bits/ 8 <0x06>;
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};
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fan@7 {
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reg = <0x04>;
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aspeed,fan-tach-ch = /bits/ 8 <0x07>;
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};
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};
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&i2c0 {
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status = "okay";
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/* Hardware monitor with temperature sensors */
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nct7802@28 {
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compatible = "nuvoton,nct7802";
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reg = <0x28>;
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#address-cells = <1>;
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#size-cells = <0>;
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channel@0 { /* LTD */
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reg = <0>;
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};
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channel@1 { /* RTD1 */
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reg = <1>;
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sensor-type = "temperature";
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temperature-mode = "thermistor";
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};
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channel@2 { /* RTD2 */
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reg = <2>;
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sensor-type = "temperature";
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temperature-mode = "thermistor";
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};
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channel@3 { /* RTD3 */
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reg = <3>;
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sensor-type = "temperature";
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};
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};
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/* Also connected to:
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* - IPMB pin header
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* - CPU #0 memory error LED @ 0x3A
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* - CPU #1 memory error LED @ 0x3C
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*/
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};
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&i2c1 {
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/* Directly connected to PCH SMBUS #0 */
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status = "okay";
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};
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&i2c2 {
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status = "okay";
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/* BMC EEPROM, incl. mainboard FRU */
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eeprom@50 {
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compatible = "atmel,24c256";
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reg = <0x50>;
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};
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/* Also connected to:
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* - fan header
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* - mini-SAS HD connector
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* - SSATA SGPIO
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* - via switch (BMC_SMB3_PCH_IE_SML3_EN, active low)
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* to PCH SMBUS #3
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*/
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};
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&i2c3 {
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status = "okay";
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/* PSU1 FRU @ 0xA0 */
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eeprom@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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};
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/* PSU2 FRU @ 0xA2 */
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eeprom@51 {
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compatible = "atmel,24c02";
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reg = <0x51>;
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};
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/* PSU1 @ 0xB0 */
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power-supply@58 {
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compatible = "pmbus";
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reg = <0x58>;
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};
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/* PSU2 @ 0xB2 */
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power-supply@59 {
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compatible = "pmbus";
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reg = <0x59>;
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};
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/* Also connected to:
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* - PCH SMBUS #1
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*/
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};
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&i2c4 {
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status = "okay";
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/* Connected to:
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* - PCH SMBUS #2
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*/
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/* Connected via switch to:
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* - CPU #0 channels ABC VDDQ @ 0x80
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* - CPU #0 channels DEF VDDQ @ 0x81
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* - CPU #1 channels ABC VDDQ @ 0x82
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* - CPU #1 channels DEF VDDQ @ 0x83
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* - CPU #0 VCCIO & VMCP @ 0x52
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* - CPU #1 VCCIO & VMCP @ 0x53
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* - CPU #0 VCCIN @ 0xC0
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* - CPU #0 VSA @ 0xC2
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* - CPU #1 VCCIN @ 0xC4
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* - CPU #1 VSA @ 0xC6
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* - J110
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*/
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};
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&i2c5 {
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status = "okay";
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/* Connected via switch (PCH_BMC_SMB_SW_P) to:
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* - mainboard FRU @ 0xAE
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* - XDP connector
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* - ME debug header
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* - clock buffer @ 0xD8
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* - i2c4 via switch (PCH_VR_SMBUS_SW_P; controlled by PCH)
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* - PCH SMBUS
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*/
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};
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&i2c6 {
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status = "okay";
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/* Connected via switch (BMC_PE_SMB_EN_1_N) to
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* bus mux (selector BMC_PE_SMB_SW_BIT[1..0]) to:
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* - 0,0: PCIE slot 1, SMB #1
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* - 0,1: PCIE slot 1, SMB #2
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* - 1,0: PCIE slot 2, SMB #1
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* - 1,1: PCIE slot 2, SMB #2
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*/
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/* Connected via switch (BMC_PE_SMB_EN_2_N) to
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* bus mux (selector BMC_PE_SMB_SW_BIT[1..0]) to:
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* - 0,0: OCP0 (A) SMB
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* - 0,1: OCP0 (C) SMB
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* - 1,0: OCP1 (A) SMB
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* - 1,1: NC
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*/
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};
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&i2c7 {
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status = "okay";
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/* Connected to:
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* - PCH SMBUS #4
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*/
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};
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&i2c8 {
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status = "okay";
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/* Not connected */
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};
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&mac0 {
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status = "okay";
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use-ncsi;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_rmii1_default>;
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};
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&mac1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
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};
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&ibt {
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status = "okay";
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};
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&kcs1 {
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status = "okay";
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aspeed,lpc-io-reg = <0xca8>;
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};
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&kcs3 {
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status = "okay";
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aspeed,lpc-io-reg = <0xca2>;
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};
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/* Enable BMC VGA output to show an early (pre-BIOS) boot screen */
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&gfx {
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status = "okay";
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memory-region = <&gfx_memory>;
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};
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/* We're following the GPIO naming as defined at
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* https://github.com/openbmc/docs/blob/master/designs/device-tree-gpio-naming.md.
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*
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* Notes on led-identify and id-button:
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* - A physical button is connected to id-button which
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* triggers the clock on a D flip-flop. The /Q output of the
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* flip-flop drives its D input.
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* - The flip-flop's Q output drives led-identify which is
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* connected to LEDs.
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* - With that, every button press toggles the LED between on and off.
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*
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* Notes on power-, reset- and nmi- button and control:
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* - The -button signals can be used to monitor physical buttons.
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* - The -control signals can be used to actuate the specific
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* operation.
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* - In hardware, the -button signals are connected to the -control
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* signals through drivers with the -control signals being
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* protected through diodes.
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*/
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&gpio {
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status = "okay";
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gpio-line-names =
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/*A0*/ "",
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/*A1*/ "",
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/*A2*/ "led-identify", /* in/out: BMC_IDLED_ON_N */
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/*A3*/ "",
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/*A4*/ "",
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/*A5*/ "",
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/*A6*/ "",
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/*A7*/ "",
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/*B0-B7*/ "","","","","","","","",
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/*C0*/ "",
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/*C1*/ "",
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/*C2*/ "",
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/*C3*/ "",
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/*C4*/ "id-button", /* in/out: BMC_IDBTN_IN_OUT_N */
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/*C5*/ "post-complete", /* in: FM_BIOS_POST_CMPLT_N */
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/*C6*/ "",
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/*C7*/ "",
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/*D0*/ "",
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/*D1*/ "",
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/*D2*/ "power-chassis-good", /* in: SYS_PWROK_BUF */
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/*D3*/ "platform-reset", /* in: SYS_PLTRST_N */
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/*D4*/ "",
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/*D5*/ "",
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/*D6*/ "",
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/*D7*/ "",
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/*E0*/ "power-button", /* in: BMC_PWBTN_IN_N */
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/*E1*/ "power-chassis-control", /* out: BMC_PWRBTN_OUT_N */
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/*E2*/ "reset-button", /* in: BMC_RSTBTN_IN_N */
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/*E3*/ "reset-control", /* out: BMC_RSTBTN_OUT_N */
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/*E4*/ "nmi-button", /* in: BMC_NMIBTN_IN_N */
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/*E5*/ "nmi-control", /* out: BMC_NMIBTN_OUT_N */
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/*E6*/ "",
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/*E7*/ "led-heartbeat", /* out: BMC_HEARTBRAT_LED_N */
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/*F0*/ "",
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/*F1*/ "clear-cmos-control", /* out: BMC_CLR_CMOS_N */
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/*F2*/ "",
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/*F3*/ "",
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/*F4*/ "led-fault", /* out: AST_HW_FAULT_N */
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/*F5*/ "",
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/*F6*/ "",
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/*F7*/ "",
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/*G0*/ "BMC_PE_SMB_EN_1_N", /* out */
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/*G1*/ "BMC_PE_SMB_EN_2_N", /* out */
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/*G2*/ "",
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/*G3*/ "",
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/*G4*/ "",
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/*G5*/ "",
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/*G6*/ "",
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/*G7*/ "",
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/*H0-H7*/ "","","","","","","","",
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/*I0-I7*/ "","","","","","","","",
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/*J0-J7*/ "","","","","","","","",
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/*K0-K7*/ "","","","","","","","",
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/*L0-L7*/ "","","","","","","","",
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/*M0-M7*/ "","","","","","","","",
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/*N0-N7*/ "","","","","","","","",
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/*O0-O7*/ "","","","","","","","",
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/*P0-P7*/ "","","","","","","","",
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/*Q0*/ "",
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/*Q1*/ "",
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/*Q2*/ "",
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/*Q3*/ "",
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/*Q4*/ "BMC_PE_SMB_SW_BIT0", /* out */
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/*Q5*/ "BMC_PE_SMB_SW_BIT1", /* out */
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/*Q6*/ "",
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/*Q7*/ "",
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/*R0-R7*/ "","","","","","","","",
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/*S0-S7*/ "","","","","","","","",
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/*T0-T7*/ "","","","","","","","",
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/*U0-U7*/ "","","","","","","","",
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/*V0-V7*/ "","","","","","","","",
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/*W0-W7*/ "","","","","","","","",
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/*X0-X7*/ "","","","","","","","",
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/*Y0-Y7*/ "","","","","","","","",
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/*Z0-Z7*/ "","","","","","","","",
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/*AA0*/ "",
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/*AA1*/ "",
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/*AA2*/ "",
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/*AA3*/ "BMC_SMB3_PCH_IE_SML3_EN", /* out */
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/*AA4*/ "",
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/*AA5*/ "",
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/*AA6*/ "",
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/*AA7*/ "",
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/*AB0-AB7*/ "","","","","","","","";
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};
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