forked from Minki/linux
75435c742b
SW reset sets DP TX to initial value, so configurations for analog parameter and interrupt are not set properly. Therefore, exynos_dp_init_analog_param() and exynos_dp_init_interrupt() should be moved to after sw reset is called, in order to set these values properly. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
1031 lines
24 KiB
C
1031 lines
24 KiB
C
/*
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* Samsung SoC DP (Display Port) interface driver.
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*
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* Copyright (C) 2012 Samsung Electronics Co., Ltd.
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* Author: Jingoo Han <jg1.han@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <video/exynos_dp.h>
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#include "exynos_dp_core.h"
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static int exynos_dp_init_dp(struct exynos_dp_device *dp)
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{
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exynos_dp_reset(dp);
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exynos_dp_swreset(dp);
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exynos_dp_init_analog_param(dp);
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exynos_dp_init_interrupt(dp);
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/* SW defined function Normal operation */
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exynos_dp_enable_sw_function(dp);
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exynos_dp_config_interrupt(dp);
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exynos_dp_init_analog_func(dp);
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exynos_dp_init_hpd(dp);
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exynos_dp_init_aux(dp);
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return 0;
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}
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static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
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{
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int timeout_loop = 0;
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exynos_dp_init_hpd(dp);
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usleep_range(200, 210);
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while (exynos_dp_get_plug_in_status(dp) != 0) {
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timeout_loop++;
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if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
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dev_err(dp->dev, "failed to get hpd plug status\n");
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return -ETIMEDOUT;
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}
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usleep_range(10, 11);
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}
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return 0;
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}
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static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
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{
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int i;
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unsigned char sum = 0;
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for (i = 0; i < EDID_BLOCK_LENGTH; i++)
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sum = sum + edid_data[i];
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return sum;
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}
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static int exynos_dp_read_edid(struct exynos_dp_device *dp)
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{
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unsigned char edid[EDID_BLOCK_LENGTH * 2];
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unsigned int extend_block = 0;
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unsigned char sum;
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unsigned char test_vector;
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int retval;
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/*
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* EDID device address is 0x50.
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* However, if necessary, you must have set upper address
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* into E-EDID in I2C device, 0x30.
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*/
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/* Read Extension Flag, Number of 128-byte EDID extension blocks */
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exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
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EDID_EXTENSION_FLAG,
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&extend_block);
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if (extend_block > 0) {
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dev_dbg(dp->dev, "EDID data includes a single extension!\n");
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/* Read EDID data */
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retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
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EDID_HEADER_PATTERN,
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EDID_BLOCK_LENGTH,
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&edid[EDID_HEADER_PATTERN]);
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if (retval != 0) {
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dev_err(dp->dev, "EDID Read failed!\n");
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return -EIO;
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}
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sum = exynos_dp_calc_edid_check_sum(edid);
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if (sum != 0) {
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dev_err(dp->dev, "EDID bad checksum!\n");
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return -EIO;
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}
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/* Read additional EDID data */
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retval = exynos_dp_read_bytes_from_i2c(dp,
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I2C_EDID_DEVICE_ADDR,
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EDID_BLOCK_LENGTH,
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EDID_BLOCK_LENGTH,
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&edid[EDID_BLOCK_LENGTH]);
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if (retval != 0) {
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dev_err(dp->dev, "EDID Read failed!\n");
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return -EIO;
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}
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sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
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if (sum != 0) {
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dev_err(dp->dev, "EDID bad checksum!\n");
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return -EIO;
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}
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exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TEST_REQUEST,
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&test_vector);
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if (test_vector & DPCD_TEST_EDID_READ) {
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exynos_dp_write_byte_to_dpcd(dp,
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DPCD_ADDR_TEST_EDID_CHECKSUM,
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edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
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exynos_dp_write_byte_to_dpcd(dp,
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DPCD_ADDR_TEST_RESPONSE,
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DPCD_TEST_EDID_CHECKSUM_WRITE);
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}
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} else {
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dev_info(dp->dev, "EDID data does not include any extensions.\n");
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/* Read EDID data */
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retval = exynos_dp_read_bytes_from_i2c(dp,
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I2C_EDID_DEVICE_ADDR,
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EDID_HEADER_PATTERN,
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EDID_BLOCK_LENGTH,
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&edid[EDID_HEADER_PATTERN]);
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if (retval != 0) {
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dev_err(dp->dev, "EDID Read failed!\n");
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return -EIO;
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}
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sum = exynos_dp_calc_edid_check_sum(edid);
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if (sum != 0) {
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dev_err(dp->dev, "EDID bad checksum!\n");
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return -EIO;
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}
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exynos_dp_read_byte_from_dpcd(dp,
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DPCD_ADDR_TEST_REQUEST,
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&test_vector);
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if (test_vector & DPCD_TEST_EDID_READ) {
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exynos_dp_write_byte_to_dpcd(dp,
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DPCD_ADDR_TEST_EDID_CHECKSUM,
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edid[EDID_CHECKSUM]);
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exynos_dp_write_byte_to_dpcd(dp,
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DPCD_ADDR_TEST_RESPONSE,
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DPCD_TEST_EDID_CHECKSUM_WRITE);
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}
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}
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dev_err(dp->dev, "EDID Read success!\n");
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return 0;
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}
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static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
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{
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u8 buf[12];
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int i;
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int retval;
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/* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
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exynos_dp_read_bytes_from_dpcd(dp,
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DPCD_ADDR_DPCD_REV,
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12, buf);
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/* Read EDID */
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for (i = 0; i < 3; i++) {
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retval = exynos_dp_read_edid(dp);
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if (retval == 0)
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break;
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}
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return retval;
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}
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static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
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bool enable)
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{
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u8 data;
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exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, &data);
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if (enable)
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exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
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DPCD_ENHANCED_FRAME_EN |
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DPCD_LANE_COUNT_SET(data));
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else
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exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
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DPCD_LANE_COUNT_SET(data));
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}
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static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
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{
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u8 data;
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int retval;
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exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data);
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retval = DPCD_ENHANCED_FRAME_CAP(data);
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return retval;
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}
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static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp)
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{
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u8 data;
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data = exynos_dp_is_enhanced_mode_available(dp);
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exynos_dp_enable_rx_to_enhanced_mode(dp, data);
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exynos_dp_enable_enhanced_mode(dp, data);
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}
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static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
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{
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exynos_dp_set_training_pattern(dp, DP_NONE);
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exynos_dp_write_byte_to_dpcd(dp,
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DPCD_ADDR_TRAINING_PATTERN_SET,
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DPCD_TRAINING_PATTERN_DISABLED);
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}
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static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
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int pre_emphasis, int lane)
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{
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switch (lane) {
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case 0:
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exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
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break;
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case 1:
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exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
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break;
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case 2:
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exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
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break;
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case 3:
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exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
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break;
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}
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}
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static void exynos_dp_link_start(struct exynos_dp_device *dp)
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{
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u8 buf[4];
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int lane;
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int lane_count;
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lane_count = dp->link_train.lane_count;
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dp->link_train.lt_state = CLOCK_RECOVERY;
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dp->link_train.eq_loop = 0;
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for (lane = 0; lane < lane_count; lane++)
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dp->link_train.cr_loop[lane] = 0;
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/* Set sink to D0 (Sink Not Ready) mode. */
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exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE,
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DPCD_SET_POWER_STATE_D0);
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/* Set link rate and count as you want to establish*/
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exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
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exynos_dp_set_lane_count(dp, dp->link_train.lane_count);
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/* Setup RX configuration */
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buf[0] = dp->link_train.link_rate;
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buf[1] = dp->link_train.lane_count;
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exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_LINK_BW_SET,
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2, buf);
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/* Set TX pre-emphasis to minimum */
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for (lane = 0; lane < lane_count; lane++)
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exynos_dp_set_lane_lane_pre_emphasis(dp,
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PRE_EMPHASIS_LEVEL_0, lane);
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/* Set training pattern 1 */
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exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
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/* Set RX training pattern */
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exynos_dp_write_byte_to_dpcd(dp,
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DPCD_ADDR_TRAINING_PATTERN_SET,
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DPCD_SCRAMBLING_DISABLED |
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DPCD_TRAINING_PATTERN_1);
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for (lane = 0; lane < lane_count; lane++)
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buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
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DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
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exynos_dp_write_bytes_to_dpcd(dp,
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DPCD_ADDR_TRAINING_LANE0_SET,
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lane_count, buf);
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}
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static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
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{
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int shift = (lane & 1) * 4;
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u8 link_value = link_status[lane>>1];
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return (link_value >> shift) & 0xf;
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}
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static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
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{
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int lane;
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u8 lane_status;
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for (lane = 0; lane < lane_count; lane++) {
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lane_status = exynos_dp_get_lane_status(link_status, lane);
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if ((lane_status & DPCD_LANE_CR_DONE) == 0)
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return -EINVAL;
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}
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return 0;
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}
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static int exynos_dp_channel_eq_ok(u8 link_align[3], int lane_count)
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{
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int lane;
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u8 lane_align;
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u8 lane_status;
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lane_align = link_align[2];
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if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
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return -EINVAL;
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for (lane = 0; lane < lane_count; lane++) {
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lane_status = exynos_dp_get_lane_status(link_align, lane);
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lane_status &= DPCD_CHANNEL_EQ_BITS;
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if (lane_status != DPCD_CHANNEL_EQ_BITS)
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return -EINVAL;
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}
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return 0;
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}
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static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
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int lane)
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{
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int shift = (lane & 1) * 4;
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u8 link_value = adjust_request[lane>>1];
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return (link_value >> shift) & 0x3;
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}
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static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
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u8 adjust_request[2],
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int lane)
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{
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int shift = (lane & 1) * 4;
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u8 link_value = adjust_request[lane>>1];
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return ((link_value >> shift) & 0xc) >> 2;
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}
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static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
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u8 training_lane_set, int lane)
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{
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switch (lane) {
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case 0:
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exynos_dp_set_lane0_link_training(dp, training_lane_set);
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break;
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case 1:
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exynos_dp_set_lane1_link_training(dp, training_lane_set);
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break;
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case 2:
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exynos_dp_set_lane2_link_training(dp, training_lane_set);
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break;
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case 3:
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exynos_dp_set_lane3_link_training(dp, training_lane_set);
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break;
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}
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}
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static unsigned int exynos_dp_get_lane_link_training(
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struct exynos_dp_device *dp,
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int lane)
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{
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u32 reg;
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switch (lane) {
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case 0:
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reg = exynos_dp_get_lane0_link_training(dp);
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break;
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case 1:
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reg = exynos_dp_get_lane1_link_training(dp);
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break;
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case 2:
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reg = exynos_dp_get_lane2_link_training(dp);
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break;
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case 3:
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reg = exynos_dp_get_lane3_link_training(dp);
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break;
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default:
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WARN_ON(1);
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return 0;
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}
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return reg;
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}
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static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
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{
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exynos_dp_training_pattern_dis(dp);
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exynos_dp_set_enhanced_mode(dp);
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dp->link_train.lt_state = FAILED;
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}
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static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
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{
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u8 link_status[2];
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int lane;
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int lane_count;
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u8 adjust_request[2];
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u8 voltage_swing;
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u8 pre_emphasis;
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u8 training_lane;
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usleep_range(100, 101);
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lane_count = dp->link_train.lane_count;
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exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
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2, link_status);
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if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
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/* set training pattern 2 for EQ */
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exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
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for (lane = 0; lane < lane_count; lane++) {
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exynos_dp_read_bytes_from_dpcd(dp,
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DPCD_ADDR_ADJUST_REQUEST_LANE0_1,
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2, adjust_request);
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voltage_swing = exynos_dp_get_adjust_request_voltage(
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adjust_request, lane);
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pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
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adjust_request, lane);
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training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
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DPCD_PRE_EMPHASIS_SET(pre_emphasis);
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if (voltage_swing == VOLTAGE_LEVEL_3)
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training_lane |= DPCD_MAX_SWING_REACHED;
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if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
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training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
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dp->link_train.training_lane[lane] = training_lane;
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exynos_dp_set_lane_link_training(dp,
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dp->link_train.training_lane[lane],
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lane);
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}
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exynos_dp_write_byte_to_dpcd(dp,
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DPCD_ADDR_TRAINING_PATTERN_SET,
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DPCD_SCRAMBLING_DISABLED |
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DPCD_TRAINING_PATTERN_2);
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exynos_dp_write_bytes_to_dpcd(dp,
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DPCD_ADDR_TRAINING_LANE0_SET,
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lane_count,
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dp->link_train.training_lane);
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dev_info(dp->dev, "Link Training Clock Recovery success\n");
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dp->link_train.lt_state = EQUALIZER_TRAINING;
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} else {
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for (lane = 0; lane < lane_count; lane++) {
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training_lane = exynos_dp_get_lane_link_training(
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dp, lane);
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exynos_dp_read_bytes_from_dpcd(dp,
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DPCD_ADDR_ADJUST_REQUEST_LANE0_1,
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2, adjust_request);
|
|
voltage_swing = exynos_dp_get_adjust_request_voltage(
|
|
adjust_request, lane);
|
|
pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
|
|
adjust_request, lane);
|
|
|
|
if (voltage_swing == VOLTAGE_LEVEL_3 ||
|
|
pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
|
|
dev_err(dp->dev, "voltage or pre emphasis reached max level\n");
|
|
goto reduce_link_rate;
|
|
}
|
|
|
|
if ((DPCD_VOLTAGE_SWING_GET(training_lane) ==
|
|
voltage_swing) &&
|
|
(DPCD_PRE_EMPHASIS_GET(training_lane) ==
|
|
pre_emphasis)) {
|
|
dp->link_train.cr_loop[lane]++;
|
|
if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP) {
|
|
dev_err(dp->dev, "CR Max loop\n");
|
|
goto reduce_link_rate;
|
|
}
|
|
}
|
|
|
|
training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
|
|
DPCD_PRE_EMPHASIS_SET(pre_emphasis);
|
|
|
|
if (voltage_swing == VOLTAGE_LEVEL_3)
|
|
training_lane |= DPCD_MAX_SWING_REACHED;
|
|
if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
|
|
training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
|
|
|
|
dp->link_train.training_lane[lane] = training_lane;
|
|
|
|
exynos_dp_set_lane_link_training(dp,
|
|
dp->link_train.training_lane[lane], lane);
|
|
}
|
|
|
|
exynos_dp_write_bytes_to_dpcd(dp,
|
|
DPCD_ADDR_TRAINING_LANE0_SET,
|
|
lane_count,
|
|
dp->link_train.training_lane);
|
|
}
|
|
|
|
return 0;
|
|
|
|
reduce_link_rate:
|
|
exynos_dp_reduce_link_rate(dp);
|
|
return -EIO;
|
|
}
|
|
|
|
static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
|
|
{
|
|
u8 link_status[2];
|
|
u8 link_align[3];
|
|
int lane;
|
|
int lane_count;
|
|
u32 reg;
|
|
|
|
u8 adjust_request[2];
|
|
u8 voltage_swing;
|
|
u8 pre_emphasis;
|
|
u8 training_lane;
|
|
|
|
usleep_range(400, 401);
|
|
|
|
lane_count = dp->link_train.lane_count;
|
|
|
|
exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
|
|
2, link_status);
|
|
|
|
if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
|
|
link_align[0] = link_status[0];
|
|
link_align[1] = link_status[1];
|
|
|
|
exynos_dp_read_byte_from_dpcd(dp,
|
|
DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED,
|
|
&link_align[2]);
|
|
|
|
for (lane = 0; lane < lane_count; lane++) {
|
|
exynos_dp_read_bytes_from_dpcd(dp,
|
|
DPCD_ADDR_ADJUST_REQUEST_LANE0_1,
|
|
2, adjust_request);
|
|
voltage_swing = exynos_dp_get_adjust_request_voltage(
|
|
adjust_request, lane);
|
|
pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
|
|
adjust_request, lane);
|
|
training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
|
|
DPCD_PRE_EMPHASIS_SET(pre_emphasis);
|
|
|
|
if (voltage_swing == VOLTAGE_LEVEL_3)
|
|
training_lane |= DPCD_MAX_SWING_REACHED;
|
|
if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
|
|
training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
|
|
|
|
dp->link_train.training_lane[lane] = training_lane;
|
|
}
|
|
|
|
if (exynos_dp_channel_eq_ok(link_status, lane_count) == 0) {
|
|
/* traing pattern Set to Normal */
|
|
exynos_dp_training_pattern_dis(dp);
|
|
|
|
dev_info(dp->dev, "Link Training success!\n");
|
|
|
|
exynos_dp_get_link_bandwidth(dp, ®);
|
|
dp->link_train.link_rate = reg;
|
|
dev_dbg(dp->dev, "final bandwidth = %.2x\n",
|
|
dp->link_train.link_rate);
|
|
|
|
exynos_dp_get_lane_count(dp, ®);
|
|
dp->link_train.lane_count = reg;
|
|
dev_dbg(dp->dev, "final lane count = %.2x\n",
|
|
dp->link_train.lane_count);
|
|
|
|
/* set enhanced mode if available */
|
|
exynos_dp_set_enhanced_mode(dp);
|
|
dp->link_train.lt_state = FINISHED;
|
|
} else {
|
|
/* not all locked */
|
|
dp->link_train.eq_loop++;
|
|
|
|
if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
|
|
dev_err(dp->dev, "EQ Max loop\n");
|
|
goto reduce_link_rate;
|
|
}
|
|
|
|
for (lane = 0; lane < lane_count; lane++)
|
|
exynos_dp_set_lane_link_training(dp,
|
|
dp->link_train.training_lane[lane],
|
|
lane);
|
|
|
|
exynos_dp_write_bytes_to_dpcd(dp,
|
|
DPCD_ADDR_TRAINING_LANE0_SET,
|
|
lane_count,
|
|
dp->link_train.training_lane);
|
|
}
|
|
} else {
|
|
goto reduce_link_rate;
|
|
}
|
|
|
|
return 0;
|
|
|
|
reduce_link_rate:
|
|
exynos_dp_reduce_link_rate(dp);
|
|
return -EIO;
|
|
}
|
|
|
|
static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
|
|
u8 *bandwidth)
|
|
{
|
|
u8 data;
|
|
|
|
/*
|
|
* For DP rev.1.1, Maximum link rate of Main Link lanes
|
|
* 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
|
|
*/
|
|
exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LINK_RATE, &data);
|
|
*bandwidth = data;
|
|
}
|
|
|
|
static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
|
|
u8 *lane_count)
|
|
{
|
|
u8 data;
|
|
|
|
/*
|
|
* For DP rev.1.1, Maximum number of Main Link lanes
|
|
* 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
|
|
*/
|
|
exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data);
|
|
*lane_count = DPCD_MAX_LANE_COUNT(data);
|
|
}
|
|
|
|
static void exynos_dp_init_training(struct exynos_dp_device *dp,
|
|
enum link_lane_count_type max_lane,
|
|
enum link_rate_type max_rate)
|
|
{
|
|
/*
|
|
* MACRO_RST must be applied after the PLL_LOCK to avoid
|
|
* the DP inter pair skew issue for at least 10 us
|
|
*/
|
|
exynos_dp_reset_macro(dp);
|
|
|
|
/* Initialize by reading RX's DPCD */
|
|
exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
|
|
exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
|
|
|
|
if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
|
|
(dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
|
|
dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
|
|
dp->link_train.link_rate);
|
|
dp->link_train.link_rate = LINK_RATE_1_62GBPS;
|
|
}
|
|
|
|
if (dp->link_train.lane_count == 0) {
|
|
dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
|
|
dp->link_train.lane_count);
|
|
dp->link_train.lane_count = (u8)LANE_COUNT1;
|
|
}
|
|
|
|
/* Setup TX lane count & rate */
|
|
if (dp->link_train.lane_count > max_lane)
|
|
dp->link_train.lane_count = max_lane;
|
|
if (dp->link_train.link_rate > max_rate)
|
|
dp->link_train.link_rate = max_rate;
|
|
|
|
/* All DP analog module power up */
|
|
exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
|
|
}
|
|
|
|
static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
|
|
{
|
|
int retval = 0;
|
|
int training_finished = 0;
|
|
|
|
dp->link_train.lt_state = START;
|
|
|
|
/* Process here */
|
|
while (!training_finished) {
|
|
switch (dp->link_train.lt_state) {
|
|
case START:
|
|
exynos_dp_link_start(dp);
|
|
break;
|
|
case CLOCK_RECOVERY:
|
|
retval = exynos_dp_process_clock_recovery(dp);
|
|
if (retval)
|
|
dev_err(dp->dev, "LT CR failed!\n");
|
|
break;
|
|
case EQUALIZER_TRAINING:
|
|
retval = exynos_dp_process_equalizer_training(dp);
|
|
if (retval)
|
|
dev_err(dp->dev, "LT EQ failed!\n");
|
|
break;
|
|
case FINISHED:
|
|
training_finished = 1;
|
|
break;
|
|
case FAILED:
|
|
return -EREMOTEIO;
|
|
}
|
|
}
|
|
|
|
return retval;
|
|
}
|
|
|
|
static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
|
|
u32 count,
|
|
u32 bwtype)
|
|
{
|
|
int i;
|
|
int retval;
|
|
|
|
for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
|
|
exynos_dp_init_training(dp, count, bwtype);
|
|
retval = exynos_dp_sw_link_training(dp);
|
|
if (retval == 0)
|
|
break;
|
|
|
|
usleep_range(100, 110);
|
|
}
|
|
|
|
return retval;
|
|
}
|
|
|
|
static int exynos_dp_config_video(struct exynos_dp_device *dp,
|
|
struct video_info *video_info)
|
|
{
|
|
int retval = 0;
|
|
int timeout_loop = 0;
|
|
int done_count = 0;
|
|
|
|
exynos_dp_config_video_slave_mode(dp, video_info);
|
|
|
|
exynos_dp_set_video_color_format(dp, video_info->color_depth,
|
|
video_info->color_space,
|
|
video_info->dynamic_range,
|
|
video_info->ycbcr_coeff);
|
|
|
|
if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
|
|
dev_err(dp->dev, "PLL is not locked yet.\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
for (;;) {
|
|
timeout_loop++;
|
|
if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0)
|
|
break;
|
|
if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
|
|
dev_err(dp->dev, "Timeout of video streamclk ok\n");
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
usleep_range(1, 2);
|
|
}
|
|
|
|
/* Set to use the register calculated M/N video */
|
|
exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
|
|
|
|
/* For video bist, Video timing must be generated by register */
|
|
exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
|
|
|
|
/* Disable video mute */
|
|
exynos_dp_enable_video_mute(dp, 0);
|
|
|
|
/* Configure video slave mode */
|
|
exynos_dp_enable_video_master(dp, 0);
|
|
|
|
/* Enable video */
|
|
exynos_dp_start_video(dp);
|
|
|
|
timeout_loop = 0;
|
|
|
|
for (;;) {
|
|
timeout_loop++;
|
|
if (exynos_dp_is_video_stream_on(dp) == 0) {
|
|
done_count++;
|
|
if (done_count > 10)
|
|
break;
|
|
} else if (done_count) {
|
|
done_count = 0;
|
|
}
|
|
if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
|
|
dev_err(dp->dev, "Timeout of video streamclk ok\n");
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
usleep_range(1000, 1001);
|
|
}
|
|
|
|
if (retval != 0)
|
|
dev_err(dp->dev, "Video stream is not detected!\n");
|
|
|
|
return retval;
|
|
}
|
|
|
|
static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
|
|
{
|
|
u8 data;
|
|
|
|
if (enable) {
|
|
exynos_dp_enable_scrambling(dp);
|
|
|
|
exynos_dp_read_byte_from_dpcd(dp,
|
|
DPCD_ADDR_TRAINING_PATTERN_SET,
|
|
&data);
|
|
exynos_dp_write_byte_to_dpcd(dp,
|
|
DPCD_ADDR_TRAINING_PATTERN_SET,
|
|
(u8)(data & ~DPCD_SCRAMBLING_DISABLED));
|
|
} else {
|
|
exynos_dp_disable_scrambling(dp);
|
|
|
|
exynos_dp_read_byte_from_dpcd(dp,
|
|
DPCD_ADDR_TRAINING_PATTERN_SET,
|
|
&data);
|
|
exynos_dp_write_byte_to_dpcd(dp,
|
|
DPCD_ADDR_TRAINING_PATTERN_SET,
|
|
(u8)(data | DPCD_SCRAMBLING_DISABLED));
|
|
}
|
|
}
|
|
|
|
static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
|
|
{
|
|
struct exynos_dp_device *dp = arg;
|
|
|
|
dev_err(dp->dev, "exynos_dp_irq_handler\n");
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int __devinit exynos_dp_probe(struct platform_device *pdev)
|
|
{
|
|
struct resource *res;
|
|
struct exynos_dp_device *dp;
|
|
struct exynos_dp_platdata *pdata;
|
|
|
|
int ret = 0;
|
|
|
|
pdata = pdev->dev.platform_data;
|
|
if (!pdata) {
|
|
dev_err(&pdev->dev, "no platform data\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
|
|
GFP_KERNEL);
|
|
if (!dp) {
|
|
dev_err(&pdev->dev, "no memory for device data\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
dp->dev = &pdev->dev;
|
|
|
|
dp->clock = devm_clk_get(&pdev->dev, "dp");
|
|
if (IS_ERR(dp->clock)) {
|
|
dev_err(&pdev->dev, "failed to get clock\n");
|
|
return PTR_ERR(dp->clock);
|
|
}
|
|
|
|
clk_enable(dp->clock);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
dp->reg_base = devm_request_and_ioremap(&pdev->dev, res);
|
|
if (!dp->reg_base) {
|
|
dev_err(&pdev->dev, "failed to ioremap\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
dp->irq = platform_get_irq(pdev, 0);
|
|
if (!dp->irq) {
|
|
dev_err(&pdev->dev, "failed to get irq\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler, 0,
|
|
"exynos-dp", dp);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to request irq\n");
|
|
return ret;
|
|
}
|
|
|
|
dp->video_info = pdata->video_info;
|
|
if (pdata->phy_init)
|
|
pdata->phy_init();
|
|
|
|
exynos_dp_init_dp(dp);
|
|
|
|
ret = exynos_dp_detect_hpd(dp);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "unable to detect hpd\n");
|
|
return ret;
|
|
}
|
|
|
|
exynos_dp_handle_edid(dp);
|
|
|
|
ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
|
|
dp->video_info->link_rate);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "unable to do link train\n");
|
|
return ret;
|
|
}
|
|
|
|
exynos_dp_enable_scramble(dp, 1);
|
|
exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
|
|
exynos_dp_enable_enhanced_mode(dp, 1);
|
|
|
|
exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
|
|
exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
|
|
|
|
exynos_dp_init_video(dp);
|
|
ret = exynos_dp_config_video(dp, dp->video_info);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "unable to config video\n");
|
|
return ret;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, dp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __devexit exynos_dp_remove(struct platform_device *pdev)
|
|
{
|
|
struct exynos_dp_platdata *pdata = pdev->dev.platform_data;
|
|
struct exynos_dp_device *dp = platform_get_drvdata(pdev);
|
|
|
|
if (pdata && pdata->phy_exit)
|
|
pdata->phy_exit();
|
|
|
|
clk_disable(dp->clock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int exynos_dp_suspend(struct device *dev)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct exynos_dp_platdata *pdata = pdev->dev.platform_data;
|
|
struct exynos_dp_device *dp = platform_get_drvdata(pdev);
|
|
|
|
if (pdata && pdata->phy_exit)
|
|
pdata->phy_exit();
|
|
|
|
clk_disable(dp->clock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int exynos_dp_resume(struct device *dev)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct exynos_dp_platdata *pdata = pdev->dev.platform_data;
|
|
struct exynos_dp_device *dp = platform_get_drvdata(pdev);
|
|
|
|
if (pdata && pdata->phy_init)
|
|
pdata->phy_init();
|
|
|
|
clk_enable(dp->clock);
|
|
|
|
exynos_dp_init_dp(dp);
|
|
|
|
exynos_dp_detect_hpd(dp);
|
|
exynos_dp_handle_edid(dp);
|
|
|
|
exynos_dp_set_link_train(dp, dp->video_info->lane_count,
|
|
dp->video_info->link_rate);
|
|
|
|
exynos_dp_enable_scramble(dp, 1);
|
|
exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
|
|
exynos_dp_enable_enhanced_mode(dp, 1);
|
|
|
|
exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
|
|
exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
|
|
|
|
exynos_dp_init_video(dp);
|
|
exynos_dp_config_video(dp, dp->video_info);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static const struct dev_pm_ops exynos_dp_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend, exynos_dp_resume)
|
|
};
|
|
|
|
static struct platform_driver exynos_dp_driver = {
|
|
.probe = exynos_dp_probe,
|
|
.remove = __devexit_p(exynos_dp_remove),
|
|
.driver = {
|
|
.name = "exynos-dp",
|
|
.owner = THIS_MODULE,
|
|
.pm = &exynos_dp_pm_ops,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(exynos_dp_driver);
|
|
|
|
MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
|
|
MODULE_DESCRIPTION("Samsung SoC DP Driver");
|
|
MODULE_LICENSE("GPL");
|