1ccea77e2a
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details [based] [from] [clk] [highbank] [c] you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 355 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Jilayne Lovejoy <opensource@jilayne.com> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190519154041.837383322@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
90 lines
2.9 KiB
C
90 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* Applied Micro X-Gene SoC Ethernet Driver
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*
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* Copyright (c) 2014, Applied Micro Circuits Corporation
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* Authors: Iyappan Subramanian <isubramanian@apm.com>
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* Keyur Chudgar <kchudgar@apm.com>
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*/
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#ifndef __XGENE_ENET_XGMAC_H__
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#define __XGENE_ENET_XGMAC_H__
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#define X2_BLOCK_ETH_MAC_CSR_OFFSET 0x3000
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#define BLOCK_AXG_MAC_OFFSET 0x0800
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#define BLOCK_AXG_STATS_OFFSET 0x0800
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#define BLOCK_AXG_MAC_CSR_OFFSET 0x2000
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#define BLOCK_PCS_OFFSET 0x3800
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#define XGENET_CONFIG_REG_ADDR 0x20
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#define XGENET_SRST_ADDR 0x00
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#define XGENET_CLKEN_ADDR 0x08
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#define CSR_CLK BIT(0)
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#define XGENET_CLK BIT(1)
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#define PCS_CLK BIT(3)
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#define AN_REF_CLK BIT(4)
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#define AN_CLK BIT(5)
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#define AD_CLK BIT(6)
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#define CSR_RST BIT(0)
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#define XGENET_RST BIT(1)
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#define PCS_RST BIT(3)
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#define AN_REF_RST BIT(4)
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#define AN_RST BIT(5)
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#define AD_RST BIT(6)
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#define AXGMAC_CONFIG_0 0x0000
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#define AXGMAC_CONFIG_1 0x0004
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#define HSTMACRST BIT(31)
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#define HSTTCTLEN BIT(31)
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#define HSTTFEN BIT(30)
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#define HSTRCTLEN BIT(29)
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#define HSTRFEN BIT(28)
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#define HSTPPEN BIT(7)
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#define HSTDRPLT64 BIT(5)
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#define HSTLENCHK BIT(3)
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#define HSTMACADR_LSW_ADDR 0x0010
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#define HSTMACADR_MSW_ADDR 0x0014
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#define HSTMAXFRAME_LENGTH_ADDR 0x0020
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#define XG_MCX_RX_DV_GATE_REG_0_ADDR 0x0004
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#define XG_MCX_ECM_CFG_0_ADDR 0x0074
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#define XG_MCX_MULTI_DPF0_ADDR 0x007c
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#define XG_MCX_MULTI_DPF1_ADDR 0x0080
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#define XG_DEF_PAUSE_THRES 0x390
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#define XG_DEF_PAUSE_OFF_THRES 0x2c0
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#define XG_RSIF_CONFIG_REG_ADDR 0x00a0
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#define XG_RSIF_CLE_BUFF_THRESH 0x3
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#define RSIF_CLE_BUFF_THRESH_SET(dst, val) xgene_set_bits(dst, val, 0, 3)
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#define XG_RSIF_CONFIG1_REG_ADDR 0x00b8
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#define XG_RSIF_PLC_CLE_BUFF_THRESH 0x1
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#define RSIF_PLC_CLE_BUFF_THRESH_SET(dst, val) xgene_set_bits(dst, val, 0, 2)
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#define XG_MCX_ECM_CONFIG0_REG_0_ADDR 0x0070
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#define XG_MCX_ICM_ECM_DROP_COUNT_REG0_ADDR 0x0124
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#define XCLE_BYPASS_REG0_ADDR 0x0160
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#define XCLE_BYPASS_REG1_ADDR 0x0164
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#define XG_CFG_BYPASS_ADDR 0x0204
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#define XG_CFG_LINK_AGGR_RESUME_0_ADDR 0x0214
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#define XG_LINK_STATUS_ADDR 0x0228
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#define XG_TSIF_MSS_REG0_ADDR 0x02a4
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#define XG_DEBUG_REG_ADDR 0x0400
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#define XG_ENET_SPARE_CFG_REG_ADDR 0x040c
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#define XG_ENET_SPARE_CFG_REG_1_ADDR 0x0410
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#define XGENET_RX_DV_GATE_REG_0_ADDR 0x0804
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#define XGENET_ECM_CONFIG0_REG_0 0x0870
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#define XGENET_ICM_ECM_DROP_COUNT_REG0 0x0924
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#define XGENET_CSR_ECM_CFG_0_ADDR 0x0880
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#define XGENET_CSR_MULTI_DPF0_ADDR 0x0888
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#define XGENET_CSR_MULTI_DPF1_ADDR 0x088c
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#define XG_RXBUF_PAUSE_THRESH 0x0020
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#define XG_MCX_ICM_CONFIG0_REG_0_ADDR 0x00e0
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#define XG_MCX_ICM_CONFIG2_REG_0_ADDR 0x00e8
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#define PCS_CONTROL_1 0x0000
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#define PCS_CTRL_PCS_RST BIT(15)
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extern const struct xgene_mac_ops xgene_xgmac_ops;
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extern const struct xgene_port_ops xgene_xgport_ops;
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#endif /* __XGENE_ENET_XGMAC_H__ */
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