Huang Rui 743538838c drm/amdgpu: revise the mode2 reset for vangogh ... PCIE MMIO bar needs to be restored firstly after the reset event triggers. So it's unable to access the registers to wait for response from SMU. Becasue the value of mmMP1_SMN_C2PMSG_90 is invalid at that moment. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2021-01-13 23:48:13 -05:00
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inc	drm/amd/pm: modify the fine grain tuning function for Renoir	2021-01-08 15:18:45 -05:00
powerplay	drm/amd/pm/powerplay/hwmgr/vega10_hwmgr: Fix worthy function headers, demote barely documented one	2021-01-11 16:09:14 -05:00
swsmu	drm/amdgpu: revise the mode2 reset for vangogh	2021-01-13 23:48:13 -05:00
amdgpu_dpm.c	drm/amdgpu: skip power profile switch in sriov	2020-12-01 15:58:54 -05:00
amdgpu_pm.c	drm/amd/pm: modify the fine grain tuning function for Renoir	2021-01-08 15:18:45 -05:00
Makefile