18b4f1a022
[WHY] Power down VPG and AFMT blocks when not in use [HOW] Create afmt31 and vpg31 structs and add necessary fields to reg list Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
163 lines
6.9 KiB
C
163 lines
6.9 KiB
C
/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DAL_DCN31_VPG_H__
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#define __DAL_DCN31_VPG_H__
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#define DCN31_VPG_FROM_VPG(vpg)\
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container_of(vpg, struct dcn31_vpg, base)
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#define VPG_DCN31_REG_LIST(id) \
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SRI(VPG_GENERIC_STATUS, VPG, id), \
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SRI(VPG_GENERIC_PACKET_ACCESS_CTRL, VPG, id), \
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SRI(VPG_GENERIC_PACKET_DATA, VPG, id), \
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SRI(VPG_GSP_FRAME_UPDATE_CTRL, VPG, id), \
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SRI(VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG, id), \
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SRI(VPG_MEM_PWR, VPG, id)
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struct dcn31_vpg_registers {
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uint32_t VPG_GENERIC_STATUS;
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uint32_t VPG_GENERIC_PACKET_ACCESS_CTRL;
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uint32_t VPG_GENERIC_PACKET_DATA;
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uint32_t VPG_GSP_FRAME_UPDATE_CTRL;
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uint32_t VPG_GSP_IMMEDIATE_UPDATE_CTRL;
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uint32_t VPG_MEM_PWR;
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};
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#define DCN31_VPG_MASK_SH_LIST(mask_sh)\
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SE_SF(VPG0_VPG_GENERIC_STATUS, VPG_GENERIC_CONFLICT_OCCURED, mask_sh),\
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SE_SF(VPG0_VPG_GENERIC_STATUS, VPG_GENERIC_CONFLICT_CLR, mask_sh),\
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SE_SF(VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL, VPG_GENERIC_DATA_INDEX, mask_sh),\
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SE_SF(VPG0_VPG_GENERIC_PACKET_DATA, VPG_GENERIC_DATA_BYTE0, mask_sh),\
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SE_SF(VPG0_VPG_GENERIC_PACKET_DATA, VPG_GENERIC_DATA_BYTE1, mask_sh),\
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SE_SF(VPG0_VPG_GENERIC_PACKET_DATA, VPG_GENERIC_DATA_BYTE2, mask_sh),\
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SE_SF(VPG0_VPG_GENERIC_PACKET_DATA, VPG_GENERIC_DATA_BYTE3, mask_sh),\
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SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC0_FRAME_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC1_FRAME_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC2_FRAME_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC3_FRAME_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC4_FRAME_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC5_FRAME_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC6_FRAME_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC7_FRAME_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC8_FRAME_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC9_FRAME_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC10_FRAME_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC11_FRAME_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC12_FRAME_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC13_FRAME_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC14_FRAME_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC0_IMMEDIATE_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC1_IMMEDIATE_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC2_IMMEDIATE_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC3_IMMEDIATE_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC4_IMMEDIATE_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC5_IMMEDIATE_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC6_IMMEDIATE_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC7_IMMEDIATE_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC8_IMMEDIATE_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC9_IMMEDIATE_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC10_IMMEDIATE_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC11_IMMEDIATE_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC12_IMMEDIATE_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC13_IMMEDIATE_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC14_IMMEDIATE_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_MEM_PWR, VPG_GSP_MEM_LIGHT_SLEEP_DIS, mask_sh),\
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SE_SF(VPG0_VPG_MEM_PWR, VPG_GSP_LIGHT_SLEEP_FORCE, mask_sh),\
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SE_SF(VPG0_VPG_MEM_PWR, VPG_GSP_MEM_PWR_STATE, mask_sh)
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#define VPG_DCN31_REG_FIELD_LIST(type) \
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type VPG_GENERIC_CONFLICT_OCCURED;\
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type VPG_GENERIC_CONFLICT_CLR;\
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type VPG_GENERIC_DATA_INDEX;\
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type VPG_GENERIC_DATA_BYTE0;\
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type VPG_GENERIC_DATA_BYTE1;\
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type VPG_GENERIC_DATA_BYTE2;\
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type VPG_GENERIC_DATA_BYTE3;\
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type VPG_GENERIC0_FRAME_UPDATE;\
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type VPG_GENERIC1_FRAME_UPDATE;\
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type VPG_GENERIC2_FRAME_UPDATE;\
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type VPG_GENERIC3_FRAME_UPDATE;\
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type VPG_GENERIC4_FRAME_UPDATE;\
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type VPG_GENERIC5_FRAME_UPDATE;\
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type VPG_GENERIC6_FRAME_UPDATE;\
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type VPG_GENERIC7_FRAME_UPDATE;\
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type VPG_GENERIC8_FRAME_UPDATE;\
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type VPG_GENERIC9_FRAME_UPDATE;\
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type VPG_GENERIC10_FRAME_UPDATE;\
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type VPG_GENERIC11_FRAME_UPDATE;\
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type VPG_GENERIC12_FRAME_UPDATE;\
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type VPG_GENERIC13_FRAME_UPDATE;\
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type VPG_GENERIC14_FRAME_UPDATE;\
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type VPG_GENERIC0_IMMEDIATE_UPDATE;\
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type VPG_GENERIC1_IMMEDIATE_UPDATE;\
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type VPG_GENERIC2_IMMEDIATE_UPDATE;\
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type VPG_GENERIC3_IMMEDIATE_UPDATE;\
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type VPG_GENERIC4_IMMEDIATE_UPDATE;\
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type VPG_GENERIC5_IMMEDIATE_UPDATE;\
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type VPG_GENERIC6_IMMEDIATE_UPDATE;\
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type VPG_GENERIC7_IMMEDIATE_UPDATE;\
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type VPG_GENERIC8_IMMEDIATE_UPDATE;\
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type VPG_GENERIC9_IMMEDIATE_UPDATE;\
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type VPG_GENERIC10_IMMEDIATE_UPDATE;\
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type VPG_GENERIC11_IMMEDIATE_UPDATE;\
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type VPG_GENERIC12_IMMEDIATE_UPDATE;\
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type VPG_GENERIC13_IMMEDIATE_UPDATE;\
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type VPG_GENERIC14_IMMEDIATE_UPDATE;\
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type VPG_GSP_MEM_LIGHT_SLEEP_DIS;\
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type VPG_GSP_LIGHT_SLEEP_FORCE;\
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type VPG_GSP_MEM_PWR_STATE
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struct dcn31_vpg_shift {
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VPG_DCN31_REG_FIELD_LIST(uint8_t);
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};
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struct dcn31_vpg_mask {
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VPG_DCN31_REG_FIELD_LIST(uint32_t);
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};
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struct dcn31_vpg {
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struct vpg base;
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const struct dcn31_vpg_registers *regs;
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const struct dcn31_vpg_shift *vpg_shift;
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const struct dcn31_vpg_mask *vpg_mask;
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};
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void vpg31_poweron(
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struct vpg *vpg);
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void vpg31_powerdown(
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struct vpg *vpg);
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void vpg31_construct(struct dcn31_vpg *vpg31,
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struct dc_context *ctx,
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uint32_t inst,
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const struct dcn31_vpg_registers *vpg_regs,
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const struct dcn31_vpg_shift *vpg_shift,
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const struct dcn31_vpg_mask *vpg_mask);
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#endif
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