Rex Zhu 680731ade5 drm/amd/pp: Export registers for read vddc on VI/Vega10 ... Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2018-02-19 14:17:49 -05:00
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smu_6_0_d.h
smu_6_0_sh_mask.h
smu_7_0_0_d.h
smu_7_0_0_sh_mask.h
smu_7_0_1_d.h	drm/amdgpu: add current_pg_status register define for smu7.1	2017-02-08 17:20:22 -05:00
smu_7_0_1_sh_mask.h	drm/amd/powerplay: add CI asics support to smumgr (v3)	2017-09-26 13:06:57 -04:00
smu_7_1_0_d.h
smu_7_1_0_enum.h
smu_7_1_0_sh_mask.h
smu_7_1_1_d.h	drm/amdgpu: read hw register to check pg status.	2017-02-13 12:43:04 -05:00
smu_7_1_1_enum.h
smu_7_1_1_sh_mask.h	drm/amdgpu: read hw register to check pg status.	2017-02-13 12:43:04 -05:00
smu_7_1_2_d.h	drm/amd/powerplay: add a new register define for APU in VI.	2017-03-29 23:54:06 -04:00
smu_7_1_2_enum.h
smu_7_1_2_sh_mask.h	drm/amdgpu: read hw register to check pg status.	2017-02-13 12:43:04 -05:00
smu_7_1_3_d.h	drm/amd/pp: Export registers for read vddc on VI/Vega10	2018-02-19 14:17:49 -05:00
smu_7_1_3_enum.h
smu_7_1_3_sh_mask.h	drm/amd/pp: Export registers for read vddc on VI/Vega10	2018-02-19 14:17:49 -05:00
smu_8_0_d.h
smu_8_0_enum.h
smu_8_0_sh_mask.h