forked from Minki/linux
4008d54e29
Commit aabcaf6ae2 ("KVM: PPC: Book3S HV P9: Move host OS save/restore
functions to built-in") added a comment in switch_pmu_to_guest
function, indicating possibility of moving PMU handling code
to perf subsystem. But perf subsystem code compilation depends upon
the enablement of CONFIG_PERF_EVENTS whereas, kvm code don't have
any dependency on this config.
Patch remove this comment as switch_pmu_to_guest functionality is
needed even if perf subsystem is disabled.
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220711034927.213192-2-kjain@linux.ibm.com
220 lines
6.1 KiB
C
220 lines
6.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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#include <asm/kvm_ppc.h>
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#include <asm/pmc.h>
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#include "book3s_hv.h"
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static void freeze_pmu(unsigned long mmcr0, unsigned long mmcra)
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{
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if (!(mmcr0 & MMCR0_FC))
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goto do_freeze;
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if (mmcra & MMCRA_SAMPLE_ENABLE)
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goto do_freeze;
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if (cpu_has_feature(CPU_FTR_ARCH_31)) {
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if (!(mmcr0 & MMCR0_PMCCEXT))
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goto do_freeze;
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if (!(mmcra & MMCRA_BHRB_DISABLE))
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goto do_freeze;
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}
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return;
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do_freeze:
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mmcr0 = MMCR0_FC;
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mmcra = 0;
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if (cpu_has_feature(CPU_FTR_ARCH_31)) {
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mmcr0 |= MMCR0_PMCCEXT;
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mmcra = MMCRA_BHRB_DISABLE;
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}
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mtspr(SPRN_MMCR0, mmcr0);
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mtspr(SPRN_MMCRA, mmcra);
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isync();
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}
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void switch_pmu_to_guest(struct kvm_vcpu *vcpu,
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struct p9_host_os_sprs *host_os_sprs)
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{
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struct lppaca *lp;
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int load_pmu = 1;
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lp = vcpu->arch.vpa.pinned_addr;
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if (lp)
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load_pmu = lp->pmcregs_in_use;
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/* Save host */
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if (ppc_get_pmu_inuse()) {
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/* POWER9, POWER10 do not implement HPMC or SPMC */
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host_os_sprs->mmcr0 = mfspr(SPRN_MMCR0);
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host_os_sprs->mmcra = mfspr(SPRN_MMCRA);
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freeze_pmu(host_os_sprs->mmcr0, host_os_sprs->mmcra);
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host_os_sprs->pmc1 = mfspr(SPRN_PMC1);
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host_os_sprs->pmc2 = mfspr(SPRN_PMC2);
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host_os_sprs->pmc3 = mfspr(SPRN_PMC3);
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host_os_sprs->pmc4 = mfspr(SPRN_PMC4);
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host_os_sprs->pmc5 = mfspr(SPRN_PMC5);
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host_os_sprs->pmc6 = mfspr(SPRN_PMC6);
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host_os_sprs->mmcr1 = mfspr(SPRN_MMCR1);
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host_os_sprs->mmcr2 = mfspr(SPRN_MMCR2);
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host_os_sprs->sdar = mfspr(SPRN_SDAR);
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host_os_sprs->siar = mfspr(SPRN_SIAR);
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host_os_sprs->sier1 = mfspr(SPRN_SIER);
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if (cpu_has_feature(CPU_FTR_ARCH_31)) {
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host_os_sprs->mmcr3 = mfspr(SPRN_MMCR3);
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host_os_sprs->sier2 = mfspr(SPRN_SIER2);
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host_os_sprs->sier3 = mfspr(SPRN_SIER3);
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}
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}
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#ifdef CONFIG_PPC_PSERIES
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/* After saving PMU, before loading guest PMU, flip pmcregs_in_use */
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if (kvmhv_on_pseries()) {
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barrier();
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get_lppaca()->pmcregs_in_use = load_pmu;
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barrier();
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}
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#endif
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/*
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* Load guest. If the VPA said the PMCs are not in use but the guest
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* tried to access them anyway, HFSCR[PM] will be set by the HFAC
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* fault so we can make forward progress.
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*/
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if (load_pmu || (vcpu->arch.hfscr & HFSCR_PM)) {
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mtspr(SPRN_PMC1, vcpu->arch.pmc[0]);
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mtspr(SPRN_PMC2, vcpu->arch.pmc[1]);
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mtspr(SPRN_PMC3, vcpu->arch.pmc[2]);
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mtspr(SPRN_PMC4, vcpu->arch.pmc[3]);
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mtspr(SPRN_PMC5, vcpu->arch.pmc[4]);
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mtspr(SPRN_PMC6, vcpu->arch.pmc[5]);
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mtspr(SPRN_MMCR1, vcpu->arch.mmcr[1]);
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mtspr(SPRN_MMCR2, vcpu->arch.mmcr[2]);
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mtspr(SPRN_SDAR, vcpu->arch.sdar);
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mtspr(SPRN_SIAR, vcpu->arch.siar);
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mtspr(SPRN_SIER, vcpu->arch.sier[0]);
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if (cpu_has_feature(CPU_FTR_ARCH_31)) {
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mtspr(SPRN_MMCR3, vcpu->arch.mmcr[3]);
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mtspr(SPRN_SIER2, vcpu->arch.sier[1]);
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mtspr(SPRN_SIER3, vcpu->arch.sier[2]);
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}
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/* Set MMCRA then MMCR0 last */
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mtspr(SPRN_MMCRA, vcpu->arch.mmcra);
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mtspr(SPRN_MMCR0, vcpu->arch.mmcr[0]);
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/* No isync necessary because we're starting counters */
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if (!vcpu->arch.nested &&
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(vcpu->arch.hfscr_permitted & HFSCR_PM))
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vcpu->arch.hfscr |= HFSCR_PM;
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}
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}
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EXPORT_SYMBOL_GPL(switch_pmu_to_guest);
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void switch_pmu_to_host(struct kvm_vcpu *vcpu,
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struct p9_host_os_sprs *host_os_sprs)
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{
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struct lppaca *lp;
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int save_pmu = 1;
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lp = vcpu->arch.vpa.pinned_addr;
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if (lp)
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save_pmu = lp->pmcregs_in_use;
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if (IS_ENABLED(CONFIG_KVM_BOOK3S_HV_NESTED_PMU_WORKAROUND)) {
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/*
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* Save pmu if this guest is capable of running nested guests.
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* This is option is for old L1s that do not set their
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* lppaca->pmcregs_in_use properly when entering their L2.
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*/
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save_pmu |= nesting_enabled(vcpu->kvm);
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}
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if (save_pmu) {
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vcpu->arch.mmcr[0] = mfspr(SPRN_MMCR0);
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vcpu->arch.mmcra = mfspr(SPRN_MMCRA);
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freeze_pmu(vcpu->arch.mmcr[0], vcpu->arch.mmcra);
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vcpu->arch.pmc[0] = mfspr(SPRN_PMC1);
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vcpu->arch.pmc[1] = mfspr(SPRN_PMC2);
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vcpu->arch.pmc[2] = mfspr(SPRN_PMC3);
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vcpu->arch.pmc[3] = mfspr(SPRN_PMC4);
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vcpu->arch.pmc[4] = mfspr(SPRN_PMC5);
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vcpu->arch.pmc[5] = mfspr(SPRN_PMC6);
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vcpu->arch.mmcr[1] = mfspr(SPRN_MMCR1);
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vcpu->arch.mmcr[2] = mfspr(SPRN_MMCR2);
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vcpu->arch.sdar = mfspr(SPRN_SDAR);
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vcpu->arch.siar = mfspr(SPRN_SIAR);
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vcpu->arch.sier[0] = mfspr(SPRN_SIER);
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if (cpu_has_feature(CPU_FTR_ARCH_31)) {
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vcpu->arch.mmcr[3] = mfspr(SPRN_MMCR3);
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vcpu->arch.sier[1] = mfspr(SPRN_SIER2);
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vcpu->arch.sier[2] = mfspr(SPRN_SIER3);
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}
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} else if (vcpu->arch.hfscr & HFSCR_PM) {
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/*
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* The guest accessed PMC SPRs without specifying they should
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* be preserved, or it cleared pmcregs_in_use after the last
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* access. Just ensure they are frozen.
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*/
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freeze_pmu(mfspr(SPRN_MMCR0), mfspr(SPRN_MMCRA));
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/*
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* Demand-fault PMU register access in the guest.
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*
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* This is used to grab the guest's VPA pmcregs_in_use value
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* and reflect it into the host's VPA in the case of a nested
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* hypervisor.
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*
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* It also avoids having to zero-out SPRs after each guest
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* exit to avoid side-channels when.
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*
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* This is cleared here when we exit the guest, so later HFSCR
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* interrupt handling can add it back to run the guest with
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* PM enabled next time.
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*/
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if (!vcpu->arch.nested)
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vcpu->arch.hfscr &= ~HFSCR_PM;
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} /* otherwise the PMU should still be frozen */
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#ifdef CONFIG_PPC_PSERIES
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if (kvmhv_on_pseries()) {
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barrier();
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get_lppaca()->pmcregs_in_use = ppc_get_pmu_inuse();
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barrier();
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}
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#endif
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if (ppc_get_pmu_inuse()) {
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mtspr(SPRN_PMC1, host_os_sprs->pmc1);
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mtspr(SPRN_PMC2, host_os_sprs->pmc2);
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mtspr(SPRN_PMC3, host_os_sprs->pmc3);
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mtspr(SPRN_PMC4, host_os_sprs->pmc4);
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mtspr(SPRN_PMC5, host_os_sprs->pmc5);
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mtspr(SPRN_PMC6, host_os_sprs->pmc6);
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mtspr(SPRN_MMCR1, host_os_sprs->mmcr1);
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mtspr(SPRN_MMCR2, host_os_sprs->mmcr2);
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mtspr(SPRN_SDAR, host_os_sprs->sdar);
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mtspr(SPRN_SIAR, host_os_sprs->siar);
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mtspr(SPRN_SIER, host_os_sprs->sier1);
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if (cpu_has_feature(CPU_FTR_ARCH_31)) {
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mtspr(SPRN_MMCR3, host_os_sprs->mmcr3);
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mtspr(SPRN_SIER2, host_os_sprs->sier2);
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mtspr(SPRN_SIER3, host_os_sprs->sier3);
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}
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/* Set MMCRA then MMCR0 last */
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mtspr(SPRN_MMCRA, host_os_sprs->mmcra);
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mtspr(SPRN_MMCR0, host_os_sprs->mmcr0);
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isync();
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}
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}
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EXPORT_SYMBOL_GPL(switch_pmu_to_host);
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