forked from Minki/linux
71783e0def
Minor locking fix for musb_hdrc on OMAP3 and OMAP2430: don't read DEVCTL without holding the spinlock, since an IRQ could come in and corrupt things. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Felipe Balbi <felipe.balbi@nokia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
336 lines
8.0 KiB
C
336 lines
8.0 KiB
C
/*
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* Copyright (C) 2005-2007 by Texas Instruments
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* Some code has been taken from tusb6010.c
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* Copyrights for that are attributable to:
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* Copyright (C) 2006 Nokia Corporation
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* Jarkko Nikula <jarkko.nikula@nokia.com>
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* Tony Lindgren <tony@atomide.com>
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*
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* This file is part of the Inventra Controller Driver for Linux.
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*
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* The Inventra Controller Driver for Linux is free software; you
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* can redistribute it and/or modify it under the terms of the GNU
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* General Public License version 2 as published by the Free Software
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* Foundation.
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*
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* The Inventra Controller Driver for Linux is distributed in
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* the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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* License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with The Inventra Controller Driver for Linux ; if not,
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* write to the Free Software Foundation, Inc., 59 Temple Place,
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* Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <asm/mach-types.h>
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#include <mach/hardware.h>
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#include <mach/mux.h>
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#include "musb_core.h"
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#include "omap2430.h"
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#ifdef CONFIG_ARCH_OMAP3430
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#define get_cpu_rev() 2
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#endif
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#define MUSB_TIMEOUT_A_WAIT_BCON 1100
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static struct timer_list musb_idle_timer;
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static void musb_do_idle(unsigned long _musb)
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{
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struct musb *musb = (void *)_musb;
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unsigned long flags;
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#ifdef CONFIG_USB_MUSB_HDRC_HCD
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u8 power;
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#endif
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u8 devctl;
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spin_lock_irqsave(&musb->lock, flags);
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devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
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switch (musb->xceiv.state) {
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case OTG_STATE_A_WAIT_BCON:
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devctl &= ~MUSB_DEVCTL_SESSION;
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musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
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devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
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if (devctl & MUSB_DEVCTL_BDEVICE) {
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musb->xceiv.state = OTG_STATE_B_IDLE;
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MUSB_DEV_MODE(musb);
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} else {
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musb->xceiv.state = OTG_STATE_A_IDLE;
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MUSB_HST_MODE(musb);
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}
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break;
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#ifdef CONFIG_USB_MUSB_HDRC_HCD
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case OTG_STATE_A_SUSPEND:
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/* finish RESUME signaling? */
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if (musb->port1_status & MUSB_PORT_STAT_RESUME) {
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power = musb_readb(musb->mregs, MUSB_POWER);
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power &= ~MUSB_POWER_RESUME;
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DBG(1, "root port resume stopped, power %02x\n", power);
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musb_writeb(musb->mregs, MUSB_POWER, power);
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musb->is_active = 1;
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musb->port1_status &= ~(USB_PORT_STAT_SUSPEND
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| MUSB_PORT_STAT_RESUME);
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musb->port1_status |= USB_PORT_STAT_C_SUSPEND << 16;
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usb_hcd_poll_rh_status(musb_to_hcd(musb));
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/* NOTE: it might really be A_WAIT_BCON ... */
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musb->xceiv.state = OTG_STATE_A_HOST;
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}
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break;
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#endif
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#ifdef CONFIG_USB_MUSB_HDRC_HCD
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case OTG_STATE_A_HOST:
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devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
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if (devctl & MUSB_DEVCTL_BDEVICE)
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musb->xceiv.state = OTG_STATE_B_IDLE;
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else
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musb->xceiv.state = OTG_STATE_A_WAIT_BCON;
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#endif
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default:
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break;
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}
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spin_unlock_irqrestore(&musb->lock, flags);
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}
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void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
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{
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unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
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static unsigned long last_timer;
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if (timeout == 0)
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timeout = default_timeout;
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/* Never idle if active, or when VBUS timeout is not set as host */
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if (musb->is_active || ((musb->a_wait_bcon == 0)
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&& (musb->xceiv.state == OTG_STATE_A_WAIT_BCON))) {
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DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
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del_timer(&musb_idle_timer);
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last_timer = jiffies;
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return;
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}
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if (time_after(last_timer, timeout)) {
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if (!timer_pending(&musb_idle_timer))
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last_timer = timeout;
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else {
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DBG(4, "Longer idle timer already pending, ignoring\n");
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return;
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}
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}
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last_timer = timeout;
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DBG(4, "%s inactive, for idle timer for %lu ms\n",
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otg_state_string(musb),
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(unsigned long)jiffies_to_msecs(timeout - jiffies));
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mod_timer(&musb_idle_timer, timeout);
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}
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void musb_platform_enable(struct musb *musb)
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{
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}
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void musb_platform_disable(struct musb *musb)
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{
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}
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static void omap_vbus_power(struct musb *musb, int is_on, int sleeping)
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{
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}
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static void omap_set_vbus(struct musb *musb, int is_on)
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{
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u8 devctl;
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/* HDRC controls CPEN, but beware current surges during device
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* connect. They can trigger transient overcurrent conditions
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* that must be ignored.
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*/
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devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
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if (is_on) {
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musb->is_active = 1;
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musb->xceiv.default_a = 1;
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musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
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devctl |= MUSB_DEVCTL_SESSION;
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MUSB_HST_MODE(musb);
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} else {
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musb->is_active = 0;
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/* NOTE: we're skipping A_WAIT_VFALL -> A_IDLE and
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* jumping right to B_IDLE...
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*/
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musb->xceiv.default_a = 0;
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musb->xceiv.state = OTG_STATE_B_IDLE;
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devctl &= ~MUSB_DEVCTL_SESSION;
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MUSB_DEV_MODE(musb);
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}
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musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
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DBG(1, "VBUS %s, devctl %02x "
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/* otg %3x conf %08x prcm %08x */ "\n",
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otg_state_string(musb),
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musb_readb(musb->mregs, MUSB_DEVCTL));
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}
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static int omap_set_power(struct otg_transceiver *x, unsigned mA)
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{
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return 0;
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}
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static int musb_platform_resume(struct musb *musb);
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int musb_platform_set_mode(struct musb *musb, u8 musb_mode)
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{
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u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
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devctl |= MUSB_DEVCTL_SESSION;
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musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
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switch (musb_mode) {
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#ifdef CONFIG_USB_MUSB_HDRC_HCD
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case MUSB_HOST:
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otg_set_host(&musb->xceiv, musb->xceiv.host);
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break;
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#endif
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#ifdef CONFIG_USB_GADGET_MUSB_HDRC
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case MUSB_PERIPHERAL:
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otg_set_peripheral(&musb->xceiv, musb->xceiv.gadget);
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break;
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#endif
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#ifdef CONFIG_USB_MUSB_OTG
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case MUSB_OTG:
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break;
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#endif
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default:
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return -EINVAL;
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}
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return 0;
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}
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int __init musb_platform_init(struct musb *musb)
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{
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u32 l;
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#if defined(CONFIG_ARCH_OMAP2430)
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omap_cfg_reg(AE5_2430_USB0HS_STP);
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#endif
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musb_platform_resume(musb);
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l = omap_readl(OTG_SYSCONFIG);
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l &= ~ENABLEWAKEUP; /* disable wakeup */
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l &= ~NOSTDBY; /* remove possible nostdby */
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l |= SMARTSTDBY; /* enable smart standby */
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l &= ~AUTOIDLE; /* disable auto idle */
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l &= ~NOIDLE; /* remove possible noidle */
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l |= SMARTIDLE; /* enable smart idle */
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l |= AUTOIDLE; /* enable auto idle */
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omap_writel(l, OTG_SYSCONFIG);
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l = omap_readl(OTG_INTERFSEL);
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l |= ULPI_12PIN;
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omap_writel(l, OTG_INTERFSEL);
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pr_debug("HS USB OTG: revision 0x%x, sysconfig 0x%02x, "
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"sysstatus 0x%x, intrfsel 0x%x, simenable 0x%x\n",
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omap_readl(OTG_REVISION), omap_readl(OTG_SYSCONFIG),
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omap_readl(OTG_SYSSTATUS), omap_readl(OTG_INTERFSEL),
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omap_readl(OTG_SIMENABLE));
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omap_vbus_power(musb, musb->board_mode == MUSB_HOST, 1);
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if (is_host_enabled(musb))
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musb->board_set_vbus = omap_set_vbus;
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if (is_peripheral_enabled(musb))
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musb->xceiv.set_power = omap_set_power;
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musb->a_wait_bcon = MUSB_TIMEOUT_A_WAIT_BCON;
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setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
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return 0;
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}
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int musb_platform_suspend(struct musb *musb)
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{
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u32 l;
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if (!musb->clock)
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return 0;
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/* in any role */
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l = omap_readl(OTG_FORCESTDBY);
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l |= ENABLEFORCE; /* enable MSTANDBY */
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omap_writel(l, OTG_FORCESTDBY);
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l = omap_readl(OTG_SYSCONFIG);
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l |= ENABLEWAKEUP; /* enable wakeup */
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omap_writel(l, OTG_SYSCONFIG);
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if (musb->xceiv.set_suspend)
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musb->xceiv.set_suspend(&musb->xceiv, 1);
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if (musb->set_clock)
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musb->set_clock(musb->clock, 0);
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else
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clk_disable(musb->clock);
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return 0;
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}
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static int musb_platform_resume(struct musb *musb)
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{
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u32 l;
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if (!musb->clock)
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return 0;
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if (musb->xceiv.set_suspend)
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musb->xceiv.set_suspend(&musb->xceiv, 0);
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if (musb->set_clock)
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musb->set_clock(musb->clock, 1);
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else
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clk_enable(musb->clock);
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l = omap_readl(OTG_SYSCONFIG);
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l &= ~ENABLEWAKEUP; /* disable wakeup */
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omap_writel(l, OTG_SYSCONFIG);
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l = omap_readl(OTG_FORCESTDBY);
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l &= ~ENABLEFORCE; /* disable MSTANDBY */
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omap_writel(l, OTG_FORCESTDBY);
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return 0;
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}
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int musb_platform_exit(struct musb *musb)
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{
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omap_vbus_power(musb, 0 /*off*/, 1);
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musb_platform_suspend(musb);
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clk_put(musb->clock);
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musb->clock = 0;
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return 0;
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}
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