forked from Minki/linux
71557d70b3
Commit 356649ab6d ("ARM: dts: rockchip: unuse the slot-node and deprecate
the supports-highspeed for dw-mmc") removed the slots but not the #xx-cells
properties describing the subnodes. Do this now.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
329 lines
7.4 KiB
Plaintext
329 lines
7.4 KiB
Plaintext
/*
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* Copyright (c) 2013 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "skeleton.dtsi"
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/ {
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interrupt-parent = <&gic>;
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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mshc0 = &emmc;
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mshc1 = &mmc0;
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mshc2 = &mmc1;
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spi0 = &spi0;
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spi1 = &spi1;
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};
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xin24m: oscillator {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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#clock-cells = <0>;
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clock-output-names = "xin24m";
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};
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L2: l2-cache-controller@10138000 {
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compatible = "arm,pl310-cache";
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reg = <0x10138000 0x1000>;
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cache-unified;
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cache-level = <2>;
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};
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scu@1013c000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0x1013c000 0x100>;
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};
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global_timer: global-timer@1013c200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x1013c200 0x20>;
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interrupts = <GIC_PPI 11 0x304>;
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clocks = <&cru CORE_PERI>;
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};
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local_timer: local-timer@1013c600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x1013c600 0x20>;
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interrupts = <GIC_PPI 13 0x304>;
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clocks = <&cru CORE_PERI>;
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};
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gic: interrupt-controller@1013d000 {
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compatible = "arm,cortex-a9-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x1013d000 0x1000>,
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<0x1013c100 0x0100>;
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};
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uart0: serial@10124000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x10124000 0x400>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <1>;
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clock-names = "baudclk", "apb_pclk";
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clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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status = "disabled";
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};
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uart1: serial@10126000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x10126000 0x400>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <1>;
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clock-names = "baudclk", "apb_pclk";
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clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
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status = "disabled";
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};
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usb_otg: usb@10180000 {
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compatible = "rockchip,rk3066-usb", "snps,dwc2";
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reg = <0x10180000 0x40000>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_OTG0>;
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clock-names = "otg";
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status = "disabled";
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};
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usb_host: usb@101c0000 {
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compatible = "snps,dwc2";
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reg = <0x101c0000 0x40000>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_OTG1>;
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clock-names = "otg";
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status = "disabled";
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};
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mmc0: dwmmc@10214000 {
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compatible = "rockchip,rk2928-dw-mshc";
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reg = <0x10214000 0x1000>;
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
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clock-names = "biu", "ciu";
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status = "disabled";
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};
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mmc1: dwmmc@10218000 {
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compatible = "rockchip,rk2928-dw-mshc";
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reg = <0x10218000 0x1000>;
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
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clock-names = "biu", "ciu";
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status = "disabled";
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};
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emmc: dwmmc@1021c000 {
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compatible = "rockchip,rk2928-dw-mshc";
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reg = <0x1021c000 0x1000>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
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clock-names = "biu", "ciu";
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status = "disabled";
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};
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pmu: pmu@20004000 {
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compatible = "rockchip,rk3066-pmu", "syscon";
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reg = <0x20004000 0x100>;
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};
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grf: grf@20008000 {
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compatible = "syscon";
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reg = <0x20008000 0x200>;
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};
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i2c0: i2c@2002d000 {
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compatible = "rockchip,rk3066-i2c";
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reg = <0x2002d000 0x1000>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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rockchip,grf = <&grf>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C0>;
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status = "disabled";
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};
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i2c1: i2c@2002f000 {
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compatible = "rockchip,rk3066-i2c";
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reg = <0x2002f000 0x1000>;
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interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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rockchip,grf = <&grf>;
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clocks = <&cru PCLK_I2C1>;
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clock-names = "i2c";
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status = "disabled";
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};
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pwm0: pwm@20030000 {
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compatible = "rockchip,rk2928-pwm";
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reg = <0x20030000 0x10>;
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#pwm-cells = <2>;
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clocks = <&cru PCLK_PWM01>;
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status = "disabled";
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};
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pwm1: pwm@20030010 {
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compatible = "rockchip,rk2928-pwm";
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reg = <0x20030010 0x10>;
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#pwm-cells = <2>;
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clocks = <&cru PCLK_PWM01>;
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status = "disabled";
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};
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wdt: watchdog@2004c000 {
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compatible = "snps,dw-wdt";
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reg = <0x2004c000 0x100>;
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clocks = <&cru PCLK_WDT>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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pwm2: pwm@20050020 {
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compatible = "rockchip,rk2928-pwm";
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reg = <0x20050020 0x10>;
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#pwm-cells = <2>;
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clocks = <&cru PCLK_PWM23>;
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status = "disabled";
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};
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pwm3: pwm@20050030 {
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compatible = "rockchip,rk2928-pwm";
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reg = <0x20050030 0x10>;
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#pwm-cells = <2>;
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clocks = <&cru PCLK_PWM23>;
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status = "disabled";
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};
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i2c2: i2c@20056000 {
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compatible = "rockchip,rk3066-i2c";
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reg = <0x20056000 0x1000>;
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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rockchip,grf = <&grf>;
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clocks = <&cru PCLK_I2C2>;
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clock-names = "i2c";
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status = "disabled";
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};
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i2c3: i2c@2005a000 {
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compatible = "rockchip,rk3066-i2c";
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reg = <0x2005a000 0x1000>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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rockchip,grf = <&grf>;
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clocks = <&cru PCLK_I2C3>;
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clock-names = "i2c";
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status = "disabled";
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};
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i2c4: i2c@2005e000 {
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compatible = "rockchip,rk3066-i2c";
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reg = <0x2005e000 0x1000>;
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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rockchip,grf = <&grf>;
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clocks = <&cru PCLK_I2C4>;
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clock-names = "i2c";
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status = "disabled";
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};
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uart2: serial@20064000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x20064000 0x400>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <1>;
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clock-names = "baudclk", "apb_pclk";
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clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
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status = "disabled";
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};
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uart3: serial@20068000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x20068000 0x400>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <1>;
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clock-names = "baudclk", "apb_pclk";
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clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
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status = "disabled";
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};
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saradc: saradc@2006c000 {
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compatible = "rockchip,saradc";
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reg = <0x2006c000 0x100>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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#io-channel-cells = <1>;
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clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
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clock-names = "saradc", "apb_pclk";
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status = "disabled";
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};
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spi0: spi@20070000 {
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compatible = "rockchip,rk3066-spi";
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clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
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clock-names = "spiclk", "apb_pclk";
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interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x20070000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi1: spi@20074000 {
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compatible = "rockchip,rk3066-spi";
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clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
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clock-names = "spiclk", "apb_pclk";
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x20074000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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