forked from Minki/linux
714d8e7e27
The main change here is a significant head.S rework that allows us to boot on machines with physical memory at a really high address without having to increase our mapped VA range. Other changes include: - AES performance boost for Cortex-A57 - AArch32 (compat) userspace with 64k pages - Cortex-A53 erratum workaround for #845719 - defconfig updates (new platforms, PCI, ...) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABCgAGBQJVLnQpAAoJELescNyEwWM03RIH/iwcDc0MBZgkwfD5cnY+29p4 m89lMDo3SyGQT4NynHSw7P3R7c3zULmI+9hmJMw/yfjjjL6m7X+vVAF3xj1Am4Al OzCqYLHyFnlRktzJ6dWeF1Ese7tWqPpxn+OCXgYNpz/r5MfF/HhlyX/qNzAQPKrw ZpDvnt44DgUfweqjTbwQUg2wkyCRjmz57MQYxDcmJStdpHIu24jWOvDIo3OJGjyS L49I9DU6DGUhkISZmmBE0T7vmKMD1BcgI7OIzX2WIqn521QT+GSLMhRxaHmK1s1V A8gaMTwpo0xFhTAt7sbw/5+2663WmfRdZI+FtduvORsoxX6KdDn7DH1NQixIm8s= =+F0I -----END PGP SIGNATURE----- Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 updates from Will Deacon: "Here are the core arm64 updates for 4.1. Highlights include a significant rework to head.S (allowing us to boot on machines with physical memory at a really high address), an AES performance boost on Cortex-A57 and the ability to run a 32-bit userspace with 64k pages (although this requires said userspace to be built with a recent binutils). The head.S rework spilt over into KVM, so there are some changes under arch/arm/ which have been acked by Marc Zyngier (KVM co-maintainer). In particular, the linker script changes caused us some issues in -next, so there are a few merge commits where we had to apply fixes on top of a stable branch. Other changes include: - AES performance boost for Cortex-A57 - AArch32 (compat) userspace with 64k pages - Cortex-A53 erratum workaround for #845719 - defconfig updates (new platforms, PCI, ...)" * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (39 commits) arm64: fix midr range for Cortex-A57 erratum 832075 arm64: errata: add workaround for cortex-a53 erratum #845719 arm64: Use bool function return values of true/false not 1/0 arm64: defconfig: updates for 4.1 arm64: Extract feature parsing code from cpu_errata.c arm64: alternative: Allow immediate branch as alternative instruction arm64: insn: Add aarch64_insn_decode_immediate ARM: kvm: round HYP section to page size instead of log2 upper bound ARM: kvm: assert on HYP section boundaries not actual code size arm64: head.S: ensure idmap_t0sz is visible arm64: pmu: add support for interrupt-affinity property dt: pmu: extend ARM PMU binding to allow for explicit interrupt affinity arm64: head.S: ensure visibility of page tables arm64: KVM: use ID map with increased VA range if required arm64: mm: increase VA range of identity map ARM: kvm: implement replacement for ld's LOG2CEIL() arm64: proc: remove unused cpu_get_pgd macro arm64: enforce x1|x2|x3 == 0 upon kernel entry as per boot protocol arm64: remove __calc_phys_offset arm64: merge __enable_mmu and __turn_mmu_on ...
45 lines
1.2 KiB
Plaintext
45 lines
1.2 KiB
Plaintext
* ARM Performance Monitor Units
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ARM cores often have a PMU for counting cpu and cache events like cache misses
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and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
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representation in the device tree should be done as under:-
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Required properties:
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- compatible : should be one of
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"arm,armv8-pmuv3"
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"arm,cortex-a17-pmu"
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"arm,cortex-a15-pmu"
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"arm,cortex-a12-pmu"
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"arm,cortex-a9-pmu"
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"arm,cortex-a8-pmu"
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"arm,cortex-a7-pmu"
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"arm,cortex-a5-pmu"
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"arm,arm11mpcore-pmu"
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"arm,arm1176-pmu"
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"arm,arm1136-pmu"
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"qcom,scorpion-pmu"
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"qcom,scorpion-mp-pmu"
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"qcom,krait-pmu"
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- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu
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interrupt (PPI) then 1 interrupt should be specified.
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Optional properties:
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- interrupt-affinity : Valid only when using SPIs, specifies a list of phandles
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to CPU nodes corresponding directly to the affinity of
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the SPIs listed in the interrupts property.
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This property should be present when there is more than
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a single SPI.
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- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
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events.
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Example:
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <100 101>;
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};
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