forked from Minki/linux
8dbc1864b7
Commit17278a91e0("MIPS: CPS: Fix r1 .set mt assembler warning") added .set MIPS_ISA_LEVEL_RAW to silence warnings about .set mt on r1, however this can result in a MOVE being encoded as a 64-bit DADDU instruction on certain version of binutils (e.g. 2.22), and reserved instruction exceptions at runtime on 32-bit hardware. Reduce the sizes of the push/pop sections to include only instructions that are part of the MT ASE or which won't convert to 64-bit instructions after .set mips64r2/mips64r6. Reported-by: Greg Ungerer <gerg@linux-m68k.org> Fixes:17278a91e0("MIPS: CPS: Fix r1 .set mt assembler warning") Signed-off-by: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@mips.com> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 4.15 Tested-by: Greg Ungerer <gerg@linux-m68k.org> Patchwork: https://patchwork.linux-mips.org/patch/18578/
635 lines
12 KiB
ArmAsm
635 lines
12 KiB
ArmAsm
/*
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* Copyright (C) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@mips.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <asm/addrspace.h>
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#include <asm/asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/asmmacro.h>
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#include <asm/cacheops.h>
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#include <asm/eva.h>
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#include <asm/mipsregs.h>
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#include <asm/mipsmtregs.h>
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#include <asm/pm.h>
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#define GCR_CPC_BASE_OFS 0x0088
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#define GCR_CL_COHERENCE_OFS 0x2008
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#define GCR_CL_ID_OFS 0x2028
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#define CPC_CL_VC_STOP_OFS 0x2020
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#define CPC_CL_VC_RUN_OFS 0x2028
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.extern mips_cm_base
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.set noreorder
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#ifdef CONFIG_64BIT
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# define STATUS_BITDEPS ST0_KX
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#else
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# define STATUS_BITDEPS 0
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#endif
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#ifdef CONFIG_MIPS_CPS_NS16550
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#define DUMP_EXCEP(name) \
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PTR_LA a0, 8f; \
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jal mips_cps_bev_dump; \
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nop; \
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TEXT(name)
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#else /* !CONFIG_MIPS_CPS_NS16550 */
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#define DUMP_EXCEP(name)
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#endif /* !CONFIG_MIPS_CPS_NS16550 */
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/*
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* Set dest to non-zero if the core supports the MT ASE, else zero. If
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* MT is not supported then branch to nomt.
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*/
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.macro has_mt dest, nomt
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mfc0 \dest, CP0_CONFIG, 1
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bgez \dest, \nomt
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mfc0 \dest, CP0_CONFIG, 2
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bgez \dest, \nomt
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mfc0 \dest, CP0_CONFIG, 3
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andi \dest, \dest, MIPS_CONF3_MT
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beqz \dest, \nomt
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nop
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.endm
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/*
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* Set dest to non-zero if the core supports MIPSr6 multithreading
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* (ie. VPs), else zero. If MIPSr6 multithreading is not supported then
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* branch to nomt.
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*/
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.macro has_vp dest, nomt
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mfc0 \dest, CP0_CONFIG, 1
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bgez \dest, \nomt
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mfc0 \dest, CP0_CONFIG, 2
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bgez \dest, \nomt
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mfc0 \dest, CP0_CONFIG, 3
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bgez \dest, \nomt
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mfc0 \dest, CP0_CONFIG, 4
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bgez \dest, \nomt
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mfc0 \dest, CP0_CONFIG, 5
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andi \dest, \dest, MIPS_CONF5_VP
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beqz \dest, \nomt
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nop
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.endm
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/* Calculate an uncached address for the CM GCRs */
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.macro cmgcrb dest
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.set push
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.set noat
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MFC0 $1, CP0_CMGCRBASE
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PTR_SLL $1, $1, 4
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PTR_LI \dest, UNCAC_BASE
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PTR_ADDU \dest, \dest, $1
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.set pop
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.endm
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.section .text.cps-vec
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.balign 0x1000
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LEAF(mips_cps_core_entry)
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/*
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* These first 4 bytes will be patched by cps_smp_setup to load the
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* CCA to use into register s0.
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*/
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.word 0
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/* Check whether we're here due to an NMI */
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mfc0 k0, CP0_STATUS
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and k0, k0, ST0_NMI
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beqz k0, not_nmi
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nop
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/* This is an NMI */
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PTR_LA k0, nmi_handler
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jr k0
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nop
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not_nmi:
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/* Setup Cause */
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li t0, CAUSEF_IV
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mtc0 t0, CP0_CAUSE
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/* Setup Status */
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li t0, ST0_CU1 | ST0_CU0 | ST0_BEV | STATUS_BITDEPS
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mtc0 t0, CP0_STATUS
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/* Skip cache & coherence setup if we're already coherent */
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cmgcrb v1
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lw s7, GCR_CL_COHERENCE_OFS(v1)
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bnez s7, 1f
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nop
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/* Initialize the L1 caches */
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jal mips_cps_cache_init
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nop
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/* Enter the coherent domain */
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li t0, 0xff
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sw t0, GCR_CL_COHERENCE_OFS(v1)
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ehb
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/* Set Kseg0 CCA to that in s0 */
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1: mfc0 t0, CP0_CONFIG
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ori t0, 0x7
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xori t0, 0x7
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or t0, t0, s0
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mtc0 t0, CP0_CONFIG
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ehb
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/* Jump to kseg0 */
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PTR_LA t0, 1f
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jr t0
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nop
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/*
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* We're up, cached & coherent. Perform any EVA initialization necessary
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* before we access memory.
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*/
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1: eva_init
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/* Retrieve boot configuration pointers */
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jal mips_cps_get_bootcfg
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nop
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/* Skip core-level init if we started up coherent */
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bnez s7, 1f
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nop
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/* Perform any further required core-level initialisation */
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jal mips_cps_core_init
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nop
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/*
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* Boot any other VPEs within this core that should be online, and
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* deactivate this VPE if it should be offline.
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*/
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move a1, t9
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jal mips_cps_boot_vpes
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move a0, v0
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/* Off we go! */
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1: PTR_L t1, VPEBOOTCFG_PC(v1)
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PTR_L gp, VPEBOOTCFG_GP(v1)
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PTR_L sp, VPEBOOTCFG_SP(v1)
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jr t1
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nop
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END(mips_cps_core_entry)
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.org 0x200
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LEAF(excep_tlbfill)
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DUMP_EXCEP("TLB Fill")
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b .
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nop
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END(excep_tlbfill)
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.org 0x280
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LEAF(excep_xtlbfill)
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DUMP_EXCEP("XTLB Fill")
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b .
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nop
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END(excep_xtlbfill)
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.org 0x300
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LEAF(excep_cache)
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DUMP_EXCEP("Cache")
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b .
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nop
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END(excep_cache)
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.org 0x380
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LEAF(excep_genex)
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DUMP_EXCEP("General")
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b .
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nop
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END(excep_genex)
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.org 0x400
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LEAF(excep_intex)
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DUMP_EXCEP("Interrupt")
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b .
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nop
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END(excep_intex)
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.org 0x480
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LEAF(excep_ejtag)
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PTR_LA k0, ejtag_debug_handler
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jr k0
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nop
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END(excep_ejtag)
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LEAF(mips_cps_core_init)
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#ifdef CONFIG_MIPS_MT_SMP
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/* Check that the core implements the MT ASE */
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has_mt t0, 3f
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.set push
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.set MIPS_ISA_LEVEL_RAW
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.set mt
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/* Only allow 1 TC per VPE to execute... */
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dmt
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/* ...and for the moment only 1 VPE */
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dvpe
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PTR_LA t1, 1f
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jr.hb t1
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nop
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/* Enter VPE configuration state */
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1: mfc0 t0, CP0_MVPCONTROL
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ori t0, t0, MVPCONTROL_VPC
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mtc0 t0, CP0_MVPCONTROL
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/* Retrieve the number of VPEs within the core */
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mfc0 t0, CP0_MVPCONF0
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srl t0, t0, MVPCONF0_PVPE_SHIFT
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andi t0, t0, (MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT)
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addiu ta3, t0, 1
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/* If there's only 1, we're done */
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beqz t0, 2f
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nop
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/* Loop through each VPE within this core */
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li ta1, 1
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1: /* Operate on the appropriate TC */
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mtc0 ta1, CP0_VPECONTROL
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ehb
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/* Bind TC to VPE (1:1 TC:VPE mapping) */
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mttc0 ta1, CP0_TCBIND
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/* Set exclusive TC, non-active, master */
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li t0, VPECONF0_MVP
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sll t1, ta1, VPECONF0_XTC_SHIFT
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or t0, t0, t1
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mttc0 t0, CP0_VPECONF0
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/* Set TC non-active, non-allocatable */
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mttc0 zero, CP0_TCSTATUS
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/* Set TC halted */
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li t0, TCHALT_H
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mttc0 t0, CP0_TCHALT
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/* Next VPE */
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addiu ta1, ta1, 1
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slt t0, ta1, ta3
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bnez t0, 1b
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nop
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/* Leave VPE configuration state */
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2: mfc0 t0, CP0_MVPCONTROL
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xori t0, t0, MVPCONTROL_VPC
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mtc0 t0, CP0_MVPCONTROL
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3: .set pop
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#endif
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jr ra
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nop
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END(mips_cps_core_init)
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/**
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* mips_cps_get_bootcfg() - retrieve boot configuration pointers
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*
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* Returns: pointer to struct core_boot_config in v0, pointer to
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* struct vpe_boot_config in v1, VPE ID in t9
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*/
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LEAF(mips_cps_get_bootcfg)
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/* Calculate a pointer to this cores struct core_boot_config */
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cmgcrb t0
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lw t0, GCR_CL_ID_OFS(t0)
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li t1, COREBOOTCFG_SIZE
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mul t0, t0, t1
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PTR_LA t1, mips_cps_core_bootcfg
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PTR_L t1, 0(t1)
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PTR_ADDU v0, t0, t1
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/* Calculate this VPEs ID. If the core doesn't support MT use 0 */
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li t9, 0
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#if defined(CONFIG_CPU_MIPSR6)
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has_vp ta2, 1f
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/*
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* Assume non-contiguous numbering. Perhaps some day we'll need
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* to handle contiguous VP numbering, but no such systems yet
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* exist.
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*/
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mfc0 t9, CP0_GLOBALNUMBER
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andi t9, t9, MIPS_GLOBALNUMBER_VP
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#elif defined(CONFIG_MIPS_MT_SMP)
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has_mt ta2, 1f
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/* Find the number of VPEs present in the core */
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mfc0 t1, CP0_MVPCONF0
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srl t1, t1, MVPCONF0_PVPE_SHIFT
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andi t1, t1, MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT
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addiu t1, t1, 1
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/* Calculate a mask for the VPE ID from EBase.CPUNum */
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clz t1, t1
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li t2, 31
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subu t1, t2, t1
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li t2, 1
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sll t1, t2, t1
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addiu t1, t1, -1
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/* Retrieve the VPE ID from EBase.CPUNum */
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mfc0 t9, $15, 1
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and t9, t9, t1
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#endif
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1: /* Calculate a pointer to this VPEs struct vpe_boot_config */
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li t1, VPEBOOTCFG_SIZE
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mul v1, t9, t1
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PTR_L ta3, COREBOOTCFG_VPECONFIG(v0)
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PTR_ADDU v1, v1, ta3
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jr ra
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nop
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END(mips_cps_get_bootcfg)
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LEAF(mips_cps_boot_vpes)
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lw ta2, COREBOOTCFG_VPEMASK(a0)
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PTR_L ta3, COREBOOTCFG_VPECONFIG(a0)
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#if defined(CONFIG_CPU_MIPSR6)
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has_vp t0, 5f
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/* Find base address of CPC */
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cmgcrb t3
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PTR_L t1, GCR_CPC_BASE_OFS(t3)
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PTR_LI t2, ~0x7fff
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and t1, t1, t2
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PTR_LI t2, UNCAC_BASE
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PTR_ADD t1, t1, t2
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/* Start any other VPs that ought to be running */
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PTR_S ta2, CPC_CL_VC_RUN_OFS(t1)
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/* Ensure this VP stops running if it shouldn't be */
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not ta2
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PTR_S ta2, CPC_CL_VC_STOP_OFS(t1)
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ehb
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#elif defined(CONFIG_MIPS_MT)
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/* If the core doesn't support MT then return */
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has_mt t0, 5f
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/* Enter VPE configuration state */
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.set push
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.set MIPS_ISA_LEVEL_RAW
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.set mt
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dvpe
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.set pop
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PTR_LA t1, 1f
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jr.hb t1
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nop
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1: mfc0 t1, CP0_MVPCONTROL
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ori t1, t1, MVPCONTROL_VPC
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mtc0 t1, CP0_MVPCONTROL
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ehb
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/* Loop through each VPE */
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move t8, ta2
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li ta1, 0
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/* Check whether the VPE should be running. If not, skip it */
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1: andi t0, ta2, 1
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beqz t0, 2f
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nop
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/* Operate on the appropriate TC */
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mfc0 t0, CP0_VPECONTROL
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ori t0, t0, VPECONTROL_TARGTC
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xori t0, t0, VPECONTROL_TARGTC
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or t0, t0, ta1
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mtc0 t0, CP0_VPECONTROL
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ehb
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.set push
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.set MIPS_ISA_LEVEL_RAW
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.set mt
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/* Skip the VPE if its TC is not halted */
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mftc0 t0, CP0_TCHALT
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beqz t0, 2f
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nop
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/* Calculate a pointer to the VPEs struct vpe_boot_config */
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li t0, VPEBOOTCFG_SIZE
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mul t0, t0, ta1
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addu t0, t0, ta3
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/* Set the TC restart PC */
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lw t1, VPEBOOTCFG_PC(t0)
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mttc0 t1, CP0_TCRESTART
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/* Set the TC stack pointer */
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lw t1, VPEBOOTCFG_SP(t0)
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mttgpr t1, sp
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/* Set the TC global pointer */
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lw t1, VPEBOOTCFG_GP(t0)
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mttgpr t1, gp
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/* Copy config from this VPE */
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mfc0 t0, CP0_CONFIG
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mttc0 t0, CP0_CONFIG
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/*
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* Copy the EVA config from this VPE if the CPU supports it.
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* CONFIG3 must exist to be running MT startup - just read it.
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*/
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mfc0 t0, CP0_CONFIG, 3
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and t0, t0, MIPS_CONF3_SC
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beqz t0, 3f
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nop
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mfc0 t0, CP0_SEGCTL0
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mttc0 t0, CP0_SEGCTL0
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mfc0 t0, CP0_SEGCTL1
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mttc0 t0, CP0_SEGCTL1
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mfc0 t0, CP0_SEGCTL2
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mttc0 t0, CP0_SEGCTL2
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3:
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/* Ensure no software interrupts are pending */
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mttc0 zero, CP0_CAUSE
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mttc0 zero, CP0_STATUS
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/* Set TC active, not interrupt exempt */
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mftc0 t0, CP0_TCSTATUS
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li t1, ~TCSTATUS_IXMT
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and t0, t0, t1
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ori t0, t0, TCSTATUS_A
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mttc0 t0, CP0_TCSTATUS
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/* Clear the TC halt bit */
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mttc0 zero, CP0_TCHALT
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/* Set VPE active */
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mftc0 t0, CP0_VPECONF0
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ori t0, t0, VPECONF0_VPA
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mttc0 t0, CP0_VPECONF0
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/* Next VPE */
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2: srl ta2, ta2, 1
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addiu ta1, ta1, 1
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bnez ta2, 1b
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nop
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/* Leave VPE configuration state */
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mfc0 t1, CP0_MVPCONTROL
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xori t1, t1, MVPCONTROL_VPC
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mtc0 t1, CP0_MVPCONTROL
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ehb
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evpe
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.set pop
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/* Check whether this VPE is meant to be running */
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li t0, 1
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sll t0, t0, a1
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and t0, t0, t8
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bnez t0, 2f
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nop
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/* This VPE should be offline, halt the TC */
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li t0, TCHALT_H
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mtc0 t0, CP0_TCHALT
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PTR_LA t0, 1f
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1: jr.hb t0
|
|
nop
|
|
|
|
2:
|
|
|
|
#endif /* CONFIG_MIPS_MT_SMP */
|
|
|
|
/* Return */
|
|
5: jr ra
|
|
nop
|
|
END(mips_cps_boot_vpes)
|
|
|
|
LEAF(mips_cps_cache_init)
|
|
/*
|
|
* Clear the bits used to index the caches. Note that the architecture
|
|
* dictates that writing to any of TagLo or TagHi selects 0 or 2 should
|
|
* be valid for all MIPS32 CPUs, even those for which said writes are
|
|
* unnecessary.
|
|
*/
|
|
mtc0 zero, CP0_TAGLO, 0
|
|
mtc0 zero, CP0_TAGHI, 0
|
|
mtc0 zero, CP0_TAGLO, 2
|
|
mtc0 zero, CP0_TAGHI, 2
|
|
ehb
|
|
|
|
/* Primary cache configuration is indicated by Config1 */
|
|
mfc0 v0, CP0_CONFIG, 1
|
|
|
|
/* Detect I-cache line size */
|
|
_EXT t0, v0, MIPS_CONF1_IL_SHF, MIPS_CONF1_IL_SZ
|
|
beqz t0, icache_done
|
|
li t1, 2
|
|
sllv t0, t1, t0
|
|
|
|
/* Detect I-cache size */
|
|
_EXT t1, v0, MIPS_CONF1_IS_SHF, MIPS_CONF1_IS_SZ
|
|
xori t2, t1, 0x7
|
|
beqz t2, 1f
|
|
li t3, 32
|
|
addiu t1, t1, 1
|
|
sllv t1, t3, t1
|
|
1: /* At this point t1 == I-cache sets per way */
|
|
_EXT t2, v0, MIPS_CONF1_IA_SHF, MIPS_CONF1_IA_SZ
|
|
addiu t2, t2, 1
|
|
mul t1, t1, t0
|
|
mul t1, t1, t2
|
|
|
|
li a0, CKSEG0
|
|
PTR_ADD a1, a0, t1
|
|
1: cache Index_Store_Tag_I, 0(a0)
|
|
PTR_ADD a0, a0, t0
|
|
bne a0, a1, 1b
|
|
nop
|
|
icache_done:
|
|
|
|
/* Detect D-cache line size */
|
|
_EXT t0, v0, MIPS_CONF1_DL_SHF, MIPS_CONF1_DL_SZ
|
|
beqz t0, dcache_done
|
|
li t1, 2
|
|
sllv t0, t1, t0
|
|
|
|
/* Detect D-cache size */
|
|
_EXT t1, v0, MIPS_CONF1_DS_SHF, MIPS_CONF1_DS_SZ
|
|
xori t2, t1, 0x7
|
|
beqz t2, 1f
|
|
li t3, 32
|
|
addiu t1, t1, 1
|
|
sllv t1, t3, t1
|
|
1: /* At this point t1 == D-cache sets per way */
|
|
_EXT t2, v0, MIPS_CONF1_DA_SHF, MIPS_CONF1_DA_SZ
|
|
addiu t2, t2, 1
|
|
mul t1, t1, t0
|
|
mul t1, t1, t2
|
|
|
|
li a0, CKSEG0
|
|
PTR_ADDU a1, a0, t1
|
|
PTR_SUBU a1, a1, t0
|
|
1: cache Index_Store_Tag_D, 0(a0)
|
|
bne a0, a1, 1b
|
|
PTR_ADD a0, a0, t0
|
|
dcache_done:
|
|
|
|
jr ra
|
|
nop
|
|
END(mips_cps_cache_init)
|
|
|
|
#if defined(CONFIG_MIPS_CPS_PM) && defined(CONFIG_CPU_PM)
|
|
|
|
/* Calculate a pointer to this CPUs struct mips_static_suspend_state */
|
|
.macro psstate dest
|
|
.set push
|
|
.set noat
|
|
lw $1, TI_CPU(gp)
|
|
sll $1, $1, LONGLOG
|
|
PTR_LA \dest, __per_cpu_offset
|
|
addu $1, $1, \dest
|
|
lw $1, 0($1)
|
|
PTR_LA \dest, cps_cpu_state
|
|
addu \dest, \dest, $1
|
|
.set pop
|
|
.endm
|
|
|
|
LEAF(mips_cps_pm_save)
|
|
/* Save CPU state */
|
|
SUSPEND_SAVE_REGS
|
|
psstate t1
|
|
SUSPEND_SAVE_STATIC
|
|
jr v0
|
|
nop
|
|
END(mips_cps_pm_save)
|
|
|
|
LEAF(mips_cps_pm_restore)
|
|
/* Restore CPU state */
|
|
psstate t1
|
|
RESUME_RESTORE_STATIC
|
|
RESUME_RESTORE_REGS_RETURN
|
|
END(mips_cps_pm_restore)
|
|
|
|
#endif /* CONFIG_MIPS_CPS_PM && CONFIG_CPU_PM */
|