forked from Minki/linux
713d136978
The I2S controller needs a clock to respond to register writes. Without this, register writes will at worst hang the CPU. In practice, I've only observed writes being dropped. Luckily, the dropped register writes historically had no effect: TEGRA_I2S_TIMING: The value we wrote was the reset default. TEGRA_I2S_FIFO_SCR: The default was for the FIFOs to request more data when one slot was empty. The requested value was for the FIFOs to request when four slots were empty. The DMA controller in the mainline kernel is configured to burst a single entry at a time into the FIFO, hence there was no issue. The only negative effect was on bus efficiency losses due to an increased number of arbitration attempts. However, in various non-upstream changes, the DMA controller now bursts four entries at a time into the FIFO. If there is only space for one entry, the data is simply dropped. In practice, this resulted in 3/4 of samples being dropped, and playback at 4x the expected rate and pitch. By fixing the clocking issue, this is solved. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Liam Girdwood <lrg@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> |
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| kirkwood | ||
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| samsung | ||
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| soc-cache.c | ||
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| soc-utils.c | ||