forked from Minki/linux
70ecb842ba
There is no point to register the cpuidle driver for the 5440 as it has only one WFI state which is the default idle function when the cpuidle driver is disabled. By disabling cpuidle we prevent to enter to the governor computation for nothing, thus saving a lot of processing time. The only drawback is the statistic via sysfs on this state which is lost but it is meaningless and it could be retrieved from the ftrace easily. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
351 lines
8.2 KiB
C
351 lines
8.2 KiB
C
/*
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* SAMSUNG EXYNOS Flattened Device Tree enabled machine
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*
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* Copyright (c) 2010-2014 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/serial_s3c.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_fdt.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <asm/cacheflush.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/memory.h>
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#include <plat/cpu.h>
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#include "common.h"
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#include "mfc.h"
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#include "regs-pmu.h"
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#define L2_AUX_VAL 0x7C470001
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#define L2_AUX_MASK 0xC200ffff
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static struct map_desc exynos4_iodesc[] __initdata = {
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{
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.virtual = (unsigned long)S3C_VA_SYS,
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.pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
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.length = SZ_64K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_TIMER,
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.pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_WATCHDOG,
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.pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_SROMC,
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.pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_SYSTIMER,
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.pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_PMU,
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.pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
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.length = SZ_64K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_COMBINER_BASE,
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.pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_GIC_CPU,
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.pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
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.length = SZ_64K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_GIC_DIST,
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.pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
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.length = SZ_64K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_CMU,
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.pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
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.length = SZ_128K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_COREPERI_BASE,
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.pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
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.length = SZ_8K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_L2CC,
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.pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_DMC0,
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.pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
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.length = SZ_64K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_DMC1,
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.pfn = __phys_to_pfn(EXYNOS4_PA_DMC1),
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.length = SZ_64K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_USB_HSPHY,
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.pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
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.length = SZ_4K,
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.type = MT_DEVICE,
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},
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};
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static struct map_desc exynos5_iodesc[] __initdata = {
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{
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.virtual = (unsigned long)S3C_VA_SYS,
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.pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
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.length = SZ_64K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_TIMER,
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.pfn = __phys_to_pfn(EXYNOS5_PA_TIMER),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_WATCHDOG,
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.pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_SROMC,
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.pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_CMU,
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.pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
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.length = 144 * SZ_1K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_PMU,
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.pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
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.length = SZ_64K,
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.type = MT_DEVICE,
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},
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};
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void exynos_restart(enum reboot_mode mode, const char *cmd)
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{
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struct device_node *np;
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u32 val = 0x1;
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void __iomem *addr = EXYNOS_SWRESET;
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if (of_machine_is_compatible("samsung,exynos5440")) {
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u32 status;
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np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
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addr = of_iomap(np, 0) + 0xbc;
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status = __raw_readl(addr);
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addr = of_iomap(np, 0) + 0xcc;
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val = __raw_readl(addr);
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val = (val & 0xffff0000) | (status & 0xffff);
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}
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__raw_writel(val, addr);
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}
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static struct platform_device exynos_cpuidle = {
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.name = "exynos_cpuidle",
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.id = -1,
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};
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void __init exynos_cpuidle_init(void)
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{
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if (soc_is_exynos5440())
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return;
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platform_device_register(&exynos_cpuidle);
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}
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void __init exynos_cpufreq_init(void)
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{
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platform_device_register_simple("exynos-cpufreq", -1, NULL, 0);
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}
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void __init exynos_init_late(void)
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{
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if (of_machine_is_compatible("samsung,exynos5440"))
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/* to be supported later */
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return;
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pm_genpd_poweroff_unused();
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exynos_pm_init();
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}
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static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
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int depth, void *data)
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{
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struct map_desc iodesc;
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__be32 *reg;
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unsigned long len;
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if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
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!of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
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return 0;
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reg = of_get_flat_dt_prop(node, "reg", &len);
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if (reg == NULL || len != (sizeof(unsigned long) * 2))
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return 0;
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iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
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iodesc.length = be32_to_cpu(reg[1]) - 1;
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iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
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iodesc.type = MT_DEVICE;
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iotable_init(&iodesc, 1);
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return 1;
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}
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/*
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* exynos_map_io
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*
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* register the standard cpu IO areas
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*/
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static void __init exynos_map_io(void)
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{
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if (soc_is_exynos4())
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iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
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if (soc_is_exynos5())
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iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
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}
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void __init exynos_init_io(void)
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{
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debug_ll_io_init();
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of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
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/* detect cpu id and rev. */
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s5p_init_cpu(S5P_VA_CHIPID);
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exynos_map_io();
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}
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struct bus_type exynos_subsys = {
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.name = "exynos-core",
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.dev_name = "exynos-core",
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};
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static int __init exynos_core_init(void)
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{
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return subsys_system_register(&exynos_subsys, NULL);
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}
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core_initcall(exynos_core_init);
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static int __init exynos4_l2x0_cache_init(void)
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{
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int ret;
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ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
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if (ret)
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return ret;
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if (IS_ENABLED(CONFIG_S5P_SLEEP)) {
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l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
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clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
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}
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return 0;
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}
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early_initcall(exynos4_l2x0_cache_init);
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static void __init exynos_dt_machine_init(void)
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{
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struct device_node *i2c_np;
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const char *i2c_compat = "samsung,s3c2440-i2c";
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unsigned int tmp;
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int id;
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/*
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* Exynos5's legacy i2c controller and new high speed i2c
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* controller have muxed interrupt sources. By default the
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* interrupts for 4-channel HS-I2C controller are enabled.
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* If node for first four channels of legacy i2c controller
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* are available then re-configure the interrupts via the
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* system register.
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*/
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if (soc_is_exynos5()) {
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for_each_compatible_node(i2c_np, NULL, i2c_compat) {
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if (of_device_is_available(i2c_np)) {
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id = of_alias_get_id(i2c_np, "i2c");
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if (id < 4) {
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tmp = readl(EXYNOS5_SYS_I2C_CFG);
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writel(tmp & ~(0x1 << id),
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EXYNOS5_SYS_I2C_CFG);
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}
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}
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}
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}
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exynos_cpuidle_init();
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exynos_cpufreq_init();
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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}
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static char const *exynos_dt_compat[] __initconst = {
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"samsung,exynos4",
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"samsung,exynos4210",
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"samsung,exynos4212",
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"samsung,exynos4412",
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"samsung,exynos5",
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"samsung,exynos5250",
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"samsung,exynos5420",
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"samsung,exynos5440",
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NULL
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};
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static void __init exynos_reserve(void)
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{
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#ifdef CONFIG_S5P_DEV_MFC
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int i;
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char *mfc_mem[] = {
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"samsung,mfc-v5",
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"samsung,mfc-v6",
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"samsung,mfc-v7",
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};
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for (i = 0; i < ARRAY_SIZE(mfc_mem); i++)
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if (of_scan_flat_dt(s5p_fdt_alloc_mfc_mem, mfc_mem[i]))
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break;
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#endif
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}
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DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
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/* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
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/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
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.smp = smp_ops(exynos_smp_ops),
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.map_io = exynos_init_io,
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.init_early = exynos_firmware_init,
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.init_machine = exynos_dt_machine_init,
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.init_late = exynos_init_late,
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.dt_compat = exynos_dt_compat,
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.restart = exynos_restart,
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.reserve = exynos_reserve,
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MACHINE_END
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