forked from Minki/linux
02a841d434
Future work will be headed in the way of separating the policy supplied by the nouveau drm module from the mechanisms provided by the driver core. There will be a couple of major classes (subdev, engine) of driver modules that have clearly defined tasks, and the further directory structure change is to reflect this. No code changes here whatsoever, aside from fixing up a couple of include file pathnames. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
418 lines
11 KiB
C
418 lines
11 KiB
C
/*
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* Copyright 2010 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_dma.h"
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#include <core/ramht.h>
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#include "nv50_display.h"
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static void
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nv50_evo_channel_del(struct nouveau_channel **pevo)
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{
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struct nouveau_channel *evo = *pevo;
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if (!evo)
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return;
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*pevo = NULL;
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nouveau_ramht_ref(NULL, &evo->ramht, evo);
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nouveau_gpuobj_channel_takedown(evo);
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nouveau_bo_unmap(evo->pushbuf_bo);
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nouveau_bo_ref(NULL, &evo->pushbuf_bo);
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if (evo->user)
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iounmap(evo->user);
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kfree(evo);
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}
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void
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nv50_evo_dmaobj_init(struct nouveau_gpuobj *obj, u32 memtype, u64 base, u64 size)
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{
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struct drm_nouveau_private *dev_priv = obj->dev->dev_private;
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u32 flags5;
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if (dev_priv->chipset < 0xc0) {
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/* not supported on 0x50, specified in format mthd */
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if (dev_priv->chipset == 0x50)
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memtype = 0;
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flags5 = 0x00010000;
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} else {
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if (memtype & 0x80000000)
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flags5 = 0x00000000; /* large pages */
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else
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flags5 = 0x00020000;
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}
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nv50_gpuobj_dma_init(obj, 0, 0x3d, base, size, NV_MEM_TARGET_VRAM,
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NV_MEM_ACCESS_RW, (memtype >> 8) & 0xff, 0);
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nv_wo32(obj, 0x14, flags5);
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dev_priv->engine.instmem.flush(obj->dev);
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}
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int
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nv50_evo_dmaobj_new(struct nouveau_channel *evo, u32 handle, u32 memtype,
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u64 base, u64 size, struct nouveau_gpuobj **pobj)
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{
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struct nv50_display *disp = nv50_display(evo->dev);
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struct nouveau_gpuobj *obj = NULL;
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int ret;
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ret = nouveau_gpuobj_new(evo->dev, disp->master, 6*4, 32, 0, &obj);
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if (ret)
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return ret;
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obj->engine = NVOBJ_ENGINE_DISPLAY;
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nv50_evo_dmaobj_init(obj, memtype, base, size);
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ret = nouveau_ramht_insert(evo, handle, obj);
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if (ret)
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goto out;
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if (pobj)
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nouveau_gpuobj_ref(obj, pobj);
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out:
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nouveau_gpuobj_ref(NULL, &obj);
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return ret;
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}
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static int
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nv50_evo_channel_new(struct drm_device *dev, int chid,
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struct nouveau_channel **pevo)
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{
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struct nv50_display *disp = nv50_display(dev);
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struct nouveau_channel *evo;
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int ret;
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evo = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL);
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if (!evo)
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return -ENOMEM;
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*pevo = evo;
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evo->id = chid;
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evo->dev = dev;
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evo->user_get = 4;
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evo->user_put = 0;
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ret = nouveau_bo_new(dev, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0, NULL,
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&evo->pushbuf_bo);
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if (ret == 0)
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ret = nouveau_bo_pin(evo->pushbuf_bo, TTM_PL_FLAG_VRAM);
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if (ret) {
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NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret);
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nv50_evo_channel_del(pevo);
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return ret;
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}
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ret = nouveau_bo_map(evo->pushbuf_bo);
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if (ret) {
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NV_ERROR(dev, "Error mapping EVO DMA push buffer: %d\n", ret);
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nv50_evo_channel_del(pevo);
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return ret;
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}
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evo->user = ioremap(pci_resource_start(dev->pdev, 0) +
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NV50_PDISPLAY_USER(evo->id), PAGE_SIZE);
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if (!evo->user) {
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NV_ERROR(dev, "Error mapping EVO control regs.\n");
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nv50_evo_channel_del(pevo);
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return -ENOMEM;
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}
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/* bind primary evo channel's ramht to the channel */
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if (disp->master && evo != disp->master)
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nouveau_ramht_ref(disp->master->ramht, &evo->ramht, NULL);
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return 0;
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}
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static int
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nv50_evo_channel_init(struct nouveau_channel *evo)
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{
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struct drm_device *dev = evo->dev;
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int id = evo->id, ret, i;
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u64 pushbuf = evo->pushbuf_bo->bo.offset;
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u32 tmp;
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tmp = nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id));
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if ((tmp & 0x009f0000) == 0x00020000)
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nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), tmp | 0x00800000);
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tmp = nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id));
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if ((tmp & 0x003f0000) == 0x00030000)
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nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), tmp | 0x00600000);
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/* initialise fifo */
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nv_wr32(dev, NV50_PDISPLAY_EVO_DMA_CB(id), pushbuf >> 8 |
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NV50_PDISPLAY_EVO_DMA_CB_LOCATION_VRAM |
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NV50_PDISPLAY_EVO_DMA_CB_VALID);
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nv_wr32(dev, NV50_PDISPLAY_EVO_UNK2(id), 0x00010000);
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nv_wr32(dev, NV50_PDISPLAY_EVO_HASH_TAG(id), id);
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nv_mask(dev, NV50_PDISPLAY_EVO_CTRL(id), NV50_PDISPLAY_EVO_CTRL_DMA,
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NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);
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nv_wr32(dev, NV50_PDISPLAY_USER_PUT(id), 0x00000000);
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nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x01000003 |
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NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);
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if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x80000000, 0x00000000)) {
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NV_ERROR(dev, "EvoCh %d init timeout: 0x%08x\n", id,
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nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)));
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return -EBUSY;
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}
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/* enable error reporting on the channel */
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nv_mask(dev, 0x610028, 0x00000000, 0x00010001 << id);
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evo->dma.max = (4096/4) - 2;
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evo->dma.max &= ~7;
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evo->dma.put = 0;
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evo->dma.cur = evo->dma.put;
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evo->dma.free = evo->dma.max - evo->dma.cur;
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ret = RING_SPACE(evo, NOUVEAU_DMA_SKIPS);
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if (ret)
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return ret;
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for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
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OUT_RING(evo, 0);
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return 0;
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}
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static void
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nv50_evo_channel_fini(struct nouveau_channel *evo)
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{
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struct drm_device *dev = evo->dev;
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int id = evo->id;
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nv_mask(dev, 0x610028, 0x00010001 << id, 0x00000000);
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nv_mask(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x00001010, 0x00001000);
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nv_wr32(dev, NV50_PDISPLAY_INTR_0, (1 << id));
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nv_mask(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x00000003, 0x00000000);
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if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x001e0000, 0x00000000)) {
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NV_ERROR(dev, "EvoCh %d takedown timeout: 0x%08x\n", id,
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nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)));
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}
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}
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void
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nv50_evo_destroy(struct drm_device *dev)
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{
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struct nv50_display *disp = nv50_display(dev);
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int i;
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for (i = 0; i < 2; i++) {
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if (disp->crtc[i].sem.bo) {
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nouveau_bo_unmap(disp->crtc[i].sem.bo);
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nouveau_bo_ref(NULL, &disp->crtc[i].sem.bo);
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}
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nv50_evo_channel_del(&disp->crtc[i].sync);
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}
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nouveau_gpuobj_ref(NULL, &disp->ntfy);
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nv50_evo_channel_del(&disp->master);
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}
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int
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nv50_evo_create(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv50_display *disp = nv50_display(dev);
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struct nouveau_gpuobj *ramht = NULL;
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struct nouveau_channel *evo;
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int ret, i, j;
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/* create primary evo channel, the one we use for modesetting
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* purporses
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*/
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ret = nv50_evo_channel_new(dev, 0, &disp->master);
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if (ret)
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return ret;
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evo = disp->master;
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/* setup object management on it, any other evo channel will
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* use this also as there's no per-channel support on the
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* hardware
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*/
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ret = nouveau_gpuobj_new(dev, NULL, 32768, 65536,
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NVOBJ_FLAG_ZERO_ALLOC, &evo->ramin);
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if (ret) {
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NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
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goto err;
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}
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ret = drm_mm_init(&evo->ramin_heap, 0, 32768);
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if (ret) {
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NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret);
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goto err;
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}
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ret = nouveau_gpuobj_new(dev, evo, 4096, 16, 0, &ramht);
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if (ret) {
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NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
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goto err;
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}
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ret = nouveau_ramht_new(dev, ramht, &evo->ramht);
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nouveau_gpuobj_ref(NULL, &ramht);
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if (ret)
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goto err;
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/* not sure exactly what this is..
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*
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* the first dword of the structure is used by nvidia to wait on
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* full completion of an EVO "update" command.
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*
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* method 0x8c on the master evo channel will fill a lot more of
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* this structure with some undefined info
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*/
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ret = nouveau_gpuobj_new(dev, disp->master, 0x1000, 0,
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NVOBJ_FLAG_ZERO_ALLOC, &disp->ntfy);
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if (ret)
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goto err;
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ret = nv50_evo_dmaobj_new(disp->master, NvEvoSync, 0x0000,
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disp->ntfy->vinst, disp->ntfy->size, NULL);
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if (ret)
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goto err;
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/* create some default objects for the scanout memtypes we support */
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ret = nv50_evo_dmaobj_new(disp->master, NvEvoVRAM, 0x0000,
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0, dev_priv->vram_size, NULL);
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if (ret)
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goto err;
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ret = nv50_evo_dmaobj_new(disp->master, NvEvoVRAM_LP, 0x80000000,
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0, dev_priv->vram_size, NULL);
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if (ret)
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goto err;
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ret = nv50_evo_dmaobj_new(disp->master, NvEvoFB32, 0x80000000 |
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(dev_priv->chipset < 0xc0 ? 0x7a00 : 0xfe00),
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0, dev_priv->vram_size, NULL);
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if (ret)
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goto err;
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ret = nv50_evo_dmaobj_new(disp->master, NvEvoFB16, 0x80000000 |
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(dev_priv->chipset < 0xc0 ? 0x7000 : 0xfe00),
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0, dev_priv->vram_size, NULL);
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if (ret)
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goto err;
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/* create "display sync" channels and other structures we need
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* to implement page flipping
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*/
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for (i = 0; i < 2; i++) {
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struct nv50_display_crtc *dispc = &disp->crtc[i];
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u64 offset;
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ret = nv50_evo_channel_new(dev, 1 + i, &dispc->sync);
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if (ret)
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goto err;
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ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
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0, 0x0000, NULL, &dispc->sem.bo);
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if (!ret) {
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ret = nouveau_bo_pin(dispc->sem.bo, TTM_PL_FLAG_VRAM);
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if (!ret)
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ret = nouveau_bo_map(dispc->sem.bo);
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if (ret)
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nouveau_bo_ref(NULL, &dispc->sem.bo);
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offset = dispc->sem.bo->bo.offset;
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}
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if (ret)
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goto err;
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ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoSync, 0x0000,
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offset, 4096, NULL);
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if (ret)
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goto err;
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ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoVRAM_LP, 0x80000000,
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0, dev_priv->vram_size, NULL);
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if (ret)
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goto err;
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ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoFB32, 0x80000000 |
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(dev_priv->chipset < 0xc0 ?
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0x7a00 : 0xfe00),
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0, dev_priv->vram_size, NULL);
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if (ret)
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goto err;
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ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoFB16, 0x80000000 |
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(dev_priv->chipset < 0xc0 ?
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0x7000 : 0xfe00),
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0, dev_priv->vram_size, NULL);
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if (ret)
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goto err;
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for (j = 0; j < 4096; j += 4)
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nouveau_bo_wr32(dispc->sem.bo, j / 4, 0x74b1e000);
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dispc->sem.offset = 0;
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}
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return 0;
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err:
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nv50_evo_destroy(dev);
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return ret;
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}
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int
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nv50_evo_init(struct drm_device *dev)
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{
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struct nv50_display *disp = nv50_display(dev);
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int ret, i;
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ret = nv50_evo_channel_init(disp->master);
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if (ret)
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return ret;
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for (i = 0; i < 2; i++) {
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ret = nv50_evo_channel_init(disp->crtc[i].sync);
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if (ret)
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return ret;
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}
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return 0;
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}
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void
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nv50_evo_fini(struct drm_device *dev)
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{
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struct nv50_display *disp = nv50_display(dev);
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int i;
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for (i = 0; i < 2; i++) {
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if (disp->crtc[i].sync)
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nv50_evo_channel_fini(disp->crtc[i].sync);
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}
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if (disp->master)
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nv50_evo_channel_fini(disp->master);
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}
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