12b8567f6f
Add xcbc(aes) offloading support. Due to xcbc algorithm design and HW implementation in CAAM, driver must still have some bytes to send to the crypto engine when ahash_final() is called - such that HW correctly uses either K2 or K3 for the last block. Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com> Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
137 lines
4.4 KiB
C
137 lines
4.4 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Shared descriptors for ahash algorithms
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*
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* Copyright 2017-2018 NXP
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*/
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#include "compat.h"
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#include "desc_constr.h"
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#include "caamhash_desc.h"
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/**
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* cnstr_shdsc_ahash - ahash shared descriptor
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* @desc: pointer to buffer used for descriptor construction
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* @adata: pointer to authentication transform definitions.
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* A split key is required for SEC Era < 6; the size of the split key
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* is specified in this case.
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* Valid algorithm values - one of OP_ALG_ALGSEL_{MD5, SHA1, SHA224,
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* SHA256, SHA384, SHA512}.
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* @state: algorithm state OP_ALG_AS_{INIT, FINALIZE, INITFINALIZE, UPDATE}
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* @digestsize: algorithm's digest size
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* @ctx_len: size of Context Register
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* @import_ctx: true if previous Context Register needs to be restored
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* must be true for ahash update and final
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* must be false for for ahash first and digest
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* @era: SEC Era
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*/
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void cnstr_shdsc_ahash(u32 * const desc, struct alginfo *adata, u32 state,
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int digestsize, int ctx_len, bool import_ctx, int era)
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{
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u32 op = adata->algtype;
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init_sh_desc(desc, HDR_SHARE_SERIAL);
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/* Append key if it has been set; ahash update excluded */
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if (state != OP_ALG_AS_UPDATE && adata->keylen) {
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u32 *skip_key_load;
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/* Skip key loading if already shared */
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skip_key_load = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
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JUMP_COND_SHRD);
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if (era < 6)
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append_key_as_imm(desc, adata->key_virt,
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adata->keylen_pad,
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adata->keylen, CLASS_2 |
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KEY_DEST_MDHA_SPLIT | KEY_ENC);
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else
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append_proto_dkp(desc, adata);
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set_jump_tgt_here(desc, skip_key_load);
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op |= OP_ALG_AAI_HMAC_PRECOMP;
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}
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/* If needed, import context from software */
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if (import_ctx)
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append_seq_load(desc, ctx_len, LDST_CLASS_2_CCB |
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LDST_SRCDST_BYTE_CONTEXT);
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/* Class 2 operation */
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append_operation(desc, op | state | OP_ALG_ENCRYPT);
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/*
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* Load from buf and/or src and write to req->result or state->context
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* Calculate remaining bytes to read
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*/
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append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
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/* Read remaining bytes */
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append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_LAST2 |
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FIFOLD_TYPE_MSG | KEY_VLF);
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/* Store class2 context bytes */
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append_seq_store(desc, digestsize, LDST_CLASS_2_CCB |
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LDST_SRCDST_BYTE_CONTEXT);
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}
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EXPORT_SYMBOL(cnstr_shdsc_ahash);
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/**
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* cnstr_shdsc_axcbc - axcbc shared descriptor
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* @desc: pointer to buffer used for descriptor construction
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* @adata: pointer to authentication transform definitions.
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* @state: algorithm state OP_ALG_AS_{INIT, FINALIZE, INITFINALIZE, UPDATE}
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* @digestsize: algorithm's digest size
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* @ctx_len: size of Context Register
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* @key_dma: I/O Virtual Address of the key
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*/
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void cnstr_shdsc_axcbc(u32 * const desc, struct alginfo *adata, u32 state,
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int digestsize, int ctx_len, dma_addr_t key_dma)
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{
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u32 *skip_key_load;
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init_sh_desc(desc, HDR_SHARE_SERIAL | HDR_SAVECTX);
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/* Skip loading of key, context if already shared */
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skip_key_load = append_jump(desc, JUMP_TEST_ALL | JUMP_COND_SHRD);
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if (state == OP_ALG_AS_INIT || state == OP_ALG_AS_INITFINAL) {
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append_key_as_imm(desc, adata->key_virt, adata->keylen,
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adata->keylen, CLASS_1 | KEY_DEST_CLASS_REG);
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} else { /* UPDATE, FINALIZE */
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/* Load K1 */
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append_key(desc, adata->key_dma, adata->keylen,
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CLASS_1 | KEY_DEST_CLASS_REG | KEY_ENC);
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/* Restore context */
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append_seq_load(desc, ctx_len, LDST_CLASS_1_CCB |
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LDST_SRCDST_BYTE_CONTEXT);
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}
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set_jump_tgt_here(desc, skip_key_load);
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/* Class 1 operation */
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append_operation(desc, adata->algtype | state | OP_ALG_ENCRYPT);
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/*
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* Load from buf and/or src and write to req->result or state->context
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* Calculate remaining bytes to read
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*/
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append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
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/* Read remaining bytes */
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append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLD_TYPE_LAST1 |
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FIFOLD_TYPE_MSG | FIFOLDST_VLF);
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/* Save context (partial hash, K2, K3) */
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append_seq_store(desc, digestsize, LDST_CLASS_1_CCB |
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LDST_SRCDST_BYTE_CONTEXT);
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if (state == OP_ALG_AS_INIT)
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/* Save K1 */
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append_fifo_store(desc, key_dma, adata->keylen,
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LDST_CLASS_1_CCB | FIFOST_TYPE_KEY_KEK);
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}
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EXPORT_SYMBOL(cnstr_shdsc_axcbc);
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MODULE_LICENSE("Dual BSD/GPL");
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MODULE_DESCRIPTION("FSL CAAM ahash descriptors support");
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MODULE_AUTHOR("NXP Semiconductors");
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