forked from Minki/linux
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
629 lines
17 KiB
C
629 lines
17 KiB
C
/*
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* linux/arch/arm/mach-omap/pm.c
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*
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* OMAP Power Management Routines
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*
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* Original code for the SA11x0:
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* Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
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*
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* Modified for the PXA250 by Nicolas Pitre:
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* Copyright (c) 2002 Monta Vista Software, Inc.
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*
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* Modified for the OMAP1510 by David Singleton:
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* Copyright (c) 2002 Monta Vista Software, Inc.
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*
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* Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/pm.h>
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#include <linux/sched.h>
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#include <linux/proc_fs.h>
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#include <linux/pm.h>
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#include <asm/io.h>
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#include <asm/mach-types.h>
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#include <asm/arch/omap16xx.h>
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#include <asm/arch/pm.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/tc.h>
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#include <asm/arch/tps65010.h>
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#include "clock.h"
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static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
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static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
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static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
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static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
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/*
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* Let's power down on idle, but only if we are really
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* idle, because once we start down the path of
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* going idle we continue to do idle even if we get
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* a clock tick interrupt . .
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*/
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void omap_pm_idle(void)
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{
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int (*func_ptr)(void) = 0;
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unsigned int mask32 = 0;
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/*
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* If the DSP is being used let's just idle the CPU, the overhead
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* to wake up from Big Sleep is big, milliseconds versus micro
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* seconds for wait for interrupt.
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*/
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local_irq_disable();
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local_fiq_disable();
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if (need_resched()) {
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local_fiq_enable();
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local_irq_enable();
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return;
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}
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mask32 = omap_readl(ARM_SYSST);
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local_fiq_enable();
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local_irq_enable();
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#if defined(CONFIG_OMAP_32K_TIMER) && defined(CONFIG_NO_IDLE_HZ)
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/* Override timer to use VST for the next cycle */
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omap_32k_timer_next_vst_interrupt();
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#endif
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if ((mask32 & DSP_IDLE) == 0) {
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__asm__ volatile ("mcr p15, 0, r0, c7, c0, 4");
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} else {
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if (cpu_is_omap1510()) {
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func_ptr = (void *)(OMAP1510_SRAM_IDLE_SUSPEND);
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} else if (cpu_is_omap1610() || cpu_is_omap1710()) {
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func_ptr = (void *)(OMAP1610_SRAM_IDLE_SUSPEND);
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} else if (cpu_is_omap5912()) {
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func_ptr = (void *)(OMAP5912_SRAM_IDLE_SUSPEND);
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}
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func_ptr();
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}
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}
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/*
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* Configuration of the wakeup event is board specific. For the
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* moment we put it into this helper function. Later it may move
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* to board specific files.
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*/
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static void omap_pm_wakeup_setup(void)
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{
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/*
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* Enable ARM XOR clock and release peripheral from reset by
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* writing 1 to PER_EN bit in ARM_RSTCT2, this is required
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* for UART configuration to use UART2 to wake up.
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*/
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omap_writel(omap_readl(ARM_IDLECT2) | ENABLE_XORCLK, ARM_IDLECT2);
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omap_writel(omap_readl(ARM_RSTCT2) | PER_EN, ARM_RSTCT2);
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omap_writew(MODEM_32K_EN, ULPD_CLOCK_CTRL);
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/*
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* Turn off all interrupts except L1-2nd level cascade,
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* and the L2 wakeup interrupts: keypad and UART2.
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*/
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omap_writel(~IRQ_LEVEL2, OMAP_IH1_MIR);
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if (cpu_is_omap1510()) {
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omap_writel(~(IRQ_UART2 | IRQ_KEYBOARD), OMAP_IH2_MIR);
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}
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if (cpu_is_omap16xx()) {
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omap_writel(~(IRQ_UART2 | IRQ_KEYBOARD), OMAP_IH2_0_MIR);
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omap_writel(~0x0, OMAP_IH2_1_MIR);
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omap_writel(~0x0, OMAP_IH2_2_MIR);
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omap_writel(~0x0, OMAP_IH2_3_MIR);
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}
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/* New IRQ agreement */
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omap_writel(1, OMAP_IH1_CONTROL);
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/* external PULL to down, bit 22 = 0 */
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omap_writel(omap_readl(PULL_DWN_CTRL_2) & ~(1<<22), PULL_DWN_CTRL_2);
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}
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void omap_pm_suspend(void)
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{
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unsigned int mask32 = 0;
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unsigned long arg0 = 0, arg1 = 0;
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int (*func_ptr)(unsigned short, unsigned short) = 0;
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unsigned short save_dsp_idlect2;
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printk("PM: OMAP%x is entering deep sleep now ...\n", system_rev);
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if (machine_is_omap_osk()) {
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/* Stop LED1 (D9) blink */
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tps65010_set_led(LED1, OFF);
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}
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/*
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* Step 1: turn off interrupts
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*/
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local_irq_disable();
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local_fiq_disable();
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/*
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* Step 2: save registers
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*
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* The omap is a strange/beautiful device. The caches, memory
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* and register state are preserved across power saves.
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* We have to save and restore very little register state to
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* idle the omap.
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*
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* Save interrupt, MPUI, ARM and UPLD control registers.
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*/
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if (cpu_is_omap1510()) {
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MPUI1510_SAVE(OMAP_IH1_MIR);
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MPUI1510_SAVE(OMAP_IH2_MIR);
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MPUI1510_SAVE(MPUI_CTRL);
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MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
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MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
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MPUI1510_SAVE(EMIFS_CONFIG);
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MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
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} else if (cpu_is_omap16xx()) {
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MPUI1610_SAVE(OMAP_IH1_MIR);
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MPUI1610_SAVE(OMAP_IH2_0_MIR);
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MPUI1610_SAVE(OMAP_IH2_1_MIR);
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MPUI1610_SAVE(OMAP_IH2_2_MIR);
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MPUI1610_SAVE(OMAP_IH2_3_MIR);
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MPUI1610_SAVE(MPUI_CTRL);
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MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
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MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
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MPUI1610_SAVE(EMIFS_CONFIG);
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MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
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}
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ARM_SAVE(ARM_CKCTL);
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ARM_SAVE(ARM_IDLECT1);
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ARM_SAVE(ARM_IDLECT2);
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ARM_SAVE(ARM_EWUPCT);
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ARM_SAVE(ARM_RSTCT1);
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ARM_SAVE(ARM_RSTCT2);
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ARM_SAVE(ARM_SYSST);
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ULPD_SAVE(ULPD_CLOCK_CTRL);
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ULPD_SAVE(ULPD_STATUS_REQ);
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/*
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* Step 3: LOW_PWR signal enabling
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*
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* Allow the LOW_PWR signal to be visible on MPUIO5 ball.
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*/
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if (cpu_is_omap1510()) {
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/* POWER_CTRL_REG = 0x1 (LOW_POWER is available) */
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omap_writew(omap_readw(ULPD_POWER_CTRL) |
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OMAP1510_ULPD_LOW_POWER_REQ, ULPD_POWER_CTRL);
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} else if (cpu_is_omap16xx()) {
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/* POWER_CTRL_REG = 0x1 (LOW_POWER is available) */
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omap_writew(omap_readw(ULPD_POWER_CTRL) |
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OMAP1610_ULPD_LOW_POWER_REQ, ULPD_POWER_CTRL);
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}
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/* configure LOW_PWR pin */
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omap_cfg_reg(T20_1610_LOW_PWR);
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/*
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* Step 4: OMAP DSP Shutdown
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*/
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/* Set DSP_RST = 1 and DSP_EN = 0, put DSP block into reset */
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omap_writel((omap_readl(ARM_RSTCT1) | DSP_RST) & ~DSP_ENABLE,
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ARM_RSTCT1);
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/* Set DSP boot mode to DSP-IDLE, DSP_BOOT_MODE = 0x2 */
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omap_writel(DSP_IDLE_MODE, MPUI_DSP_BOOT_CONFIG);
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/* Set EN_DSPCK = 0, stop DSP block clock */
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omap_writel(omap_readl(ARM_CKCTL) & ~DSP_CLOCK_ENABLE, ARM_CKCTL);
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/* Stop any DSP domain clocks */
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omap_writel(omap_readl(ARM_IDLECT2) | (1<<EN_APICK), ARM_IDLECT2);
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save_dsp_idlect2 = __raw_readw(DSP_IDLECT2);
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__raw_writew(0, DSP_IDLECT2);
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/*
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* Step 5: Wakeup Event Setup
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*/
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omap_pm_wakeup_setup();
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/*
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* Step 6a: ARM and Traffic controller shutdown
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*
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* Step 6 starts here with clock and watchdog disable
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*/
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/* stop clocks */
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mask32 = omap_readl(ARM_IDLECT2);
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mask32 &= ~(1<<EN_WDTCK); /* bit 0 -> 0 (WDT clock) */
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mask32 |= (1<<EN_XORPCK); /* bit 1 -> 1 (XORPCK clock) */
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mask32 &= ~(1<<EN_PERCK); /* bit 2 -> 0 (MPUPER_CK clock) */
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mask32 &= ~(1<<EN_LCDCK); /* bit 3 -> 0 (LCDC clock) */
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mask32 &= ~(1<<EN_LBCK); /* bit 4 -> 0 (local bus clock) */
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mask32 |= (1<<EN_APICK); /* bit 6 -> 1 (MPUI clock) */
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mask32 &= ~(1<<EN_TIMCK); /* bit 7 -> 0 (MPU timer clock) */
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mask32 &= ~(1<<DMACK_REQ); /* bit 8 -> 0 (DMAC clock) */
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mask32 &= ~(1<<EN_GPIOCK); /* bit 9 -> 0 (GPIO clock) */
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omap_writel(mask32, ARM_IDLECT2);
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/* disable ARM watchdog */
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omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
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omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
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/*
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* Step 6b: ARM and Traffic controller shutdown
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*
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* Step 6 continues here. Prepare jump to power management
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* assembly code in internal SRAM.
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*
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* Since the omap_cpu_suspend routine has been copied to
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* SRAM, we'll do an indirect procedure call to it and pass the
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* contents of arm_idlect1 and arm_idlect2 so it can restore
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* them when it wakes up and it will return.
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*/
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arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
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arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
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if (cpu_is_omap1510()) {
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func_ptr = (void *)(OMAP1510_SRAM_API_SUSPEND);
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} else if (cpu_is_omap1610() || cpu_is_omap1710()) {
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func_ptr = (void *)(OMAP1610_SRAM_API_SUSPEND);
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} else if (cpu_is_omap5912()) {
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func_ptr = (void *)(OMAP5912_SRAM_API_SUSPEND);
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}
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/*
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* Step 6c: ARM and Traffic controller shutdown
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*
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* Jump to assembly code. The processor will stay there
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* until wake up.
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*/
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func_ptr(arg0, arg1);
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/*
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* If we are here, processor is woken up!
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*/
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if (cpu_is_omap1510()) {
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/* POWER_CTRL_REG = 0x0 (LOW_POWER is disabled) */
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omap_writew(omap_readw(ULPD_POWER_CTRL) &
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~OMAP1510_ULPD_LOW_POWER_REQ, ULPD_POWER_CTRL);
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} else if (cpu_is_omap16xx()) {
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/* POWER_CTRL_REG = 0x0 (LOW_POWER is disabled) */
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omap_writew(omap_readw(ULPD_POWER_CTRL) &
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~OMAP1610_ULPD_LOW_POWER_REQ, ULPD_POWER_CTRL);
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}
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/* Restore DSP clocks */
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omap_writel(omap_readl(ARM_IDLECT2) | (1<<EN_APICK), ARM_IDLECT2);
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__raw_writew(save_dsp_idlect2, DSP_IDLECT2);
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ARM_RESTORE(ARM_IDLECT2);
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/*
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* Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
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*/
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ARM_RESTORE(ARM_CKCTL);
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ARM_RESTORE(ARM_EWUPCT);
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ARM_RESTORE(ARM_RSTCT1);
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ARM_RESTORE(ARM_RSTCT2);
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ARM_RESTORE(ARM_SYSST);
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ULPD_RESTORE(ULPD_CLOCK_CTRL);
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ULPD_RESTORE(ULPD_STATUS_REQ);
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if (cpu_is_omap1510()) {
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MPUI1510_RESTORE(MPUI_CTRL);
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MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
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MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
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MPUI1510_RESTORE(EMIFS_CONFIG);
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MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
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MPUI1510_RESTORE(OMAP_IH1_MIR);
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MPUI1510_RESTORE(OMAP_IH2_MIR);
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} else if (cpu_is_omap16xx()) {
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MPUI1610_RESTORE(MPUI_CTRL);
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MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
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MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
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MPUI1610_RESTORE(EMIFS_CONFIG);
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MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
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MPUI1610_RESTORE(OMAP_IH1_MIR);
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MPUI1610_RESTORE(OMAP_IH2_0_MIR);
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MPUI1610_RESTORE(OMAP_IH2_1_MIR);
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MPUI1610_RESTORE(OMAP_IH2_2_MIR);
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MPUI1610_RESTORE(OMAP_IH2_3_MIR);
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}
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/*
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* Reenable interrupts
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*/
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local_irq_enable();
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local_fiq_enable();
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printk("PM: OMAP%x is re-starting from deep sleep...\n", system_rev);
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if (machine_is_omap_osk()) {
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/* Let LED1 (D9) blink again */
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tps65010_set_led(LED1, BLINK);
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}
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}
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#if defined(DEBUG) && defined(CONFIG_PROC_FS)
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static int g_read_completed;
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/*
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* Read system PM registers for debugging
|
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*/
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static int omap_pm_read_proc(
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char *page_buffer,
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char **my_first_byte,
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off_t virtual_start,
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int length,
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int *eof,
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void *data)
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{
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int my_buffer_offset = 0;
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char * const my_base = page_buffer;
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ARM_SAVE(ARM_CKCTL);
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ARM_SAVE(ARM_IDLECT1);
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ARM_SAVE(ARM_IDLECT2);
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ARM_SAVE(ARM_EWUPCT);
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ARM_SAVE(ARM_RSTCT1);
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ARM_SAVE(ARM_RSTCT2);
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ARM_SAVE(ARM_SYSST);
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ULPD_SAVE(ULPD_IT_STATUS);
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ULPD_SAVE(ULPD_CLOCK_CTRL);
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ULPD_SAVE(ULPD_SOFT_REQ);
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ULPD_SAVE(ULPD_STATUS_REQ);
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ULPD_SAVE(ULPD_DPLL_CTRL);
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ULPD_SAVE(ULPD_POWER_CTRL);
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if (cpu_is_omap1510()) {
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MPUI1510_SAVE(MPUI_CTRL);
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MPUI1510_SAVE(MPUI_DSP_STATUS);
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MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
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MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
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MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
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MPUI1510_SAVE(EMIFS_CONFIG);
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} else if (cpu_is_omap16xx()) {
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MPUI1610_SAVE(MPUI_CTRL);
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MPUI1610_SAVE(MPUI_DSP_STATUS);
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MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
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MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
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MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
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MPUI1610_SAVE(EMIFS_CONFIG);
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}
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|
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if (virtual_start == 0) {
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g_read_completed = 0;
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my_buffer_offset += sprintf(my_base + my_buffer_offset,
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"ARM_CKCTL_REG: 0x%-8x \n"
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"ARM_IDLECT1_REG: 0x%-8x \n"
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"ARM_IDLECT2_REG: 0x%-8x \n"
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"ARM_EWUPCT_REG: 0x%-8x \n"
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"ARM_RSTCT1_REG: 0x%-8x \n"
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"ARM_RSTCT2_REG: 0x%-8x \n"
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"ARM_SYSST_REG: 0x%-8x \n"
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"ULPD_IT_STATUS_REG: 0x%-4x \n"
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"ULPD_CLOCK_CTRL_REG: 0x%-4x \n"
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"ULPD_SOFT_REQ_REG: 0x%-4x \n"
|
|
"ULPD_DPLL_CTRL_REG: 0x%-4x \n"
|
|
"ULPD_STATUS_REQ_REG: 0x%-4x \n"
|
|
"ULPD_POWER_CTRL_REG: 0x%-4x \n",
|
|
ARM_SHOW(ARM_CKCTL),
|
|
ARM_SHOW(ARM_IDLECT1),
|
|
ARM_SHOW(ARM_IDLECT2),
|
|
ARM_SHOW(ARM_EWUPCT),
|
|
ARM_SHOW(ARM_RSTCT1),
|
|
ARM_SHOW(ARM_RSTCT2),
|
|
ARM_SHOW(ARM_SYSST),
|
|
ULPD_SHOW(ULPD_IT_STATUS),
|
|
ULPD_SHOW(ULPD_CLOCK_CTRL),
|
|
ULPD_SHOW(ULPD_SOFT_REQ),
|
|
ULPD_SHOW(ULPD_DPLL_CTRL),
|
|
ULPD_SHOW(ULPD_STATUS_REQ),
|
|
ULPD_SHOW(ULPD_POWER_CTRL));
|
|
|
|
if (cpu_is_omap1510()) {
|
|
my_buffer_offset += sprintf(my_base + my_buffer_offset,
|
|
"MPUI1510_CTRL_REG 0x%-8x \n"
|
|
"MPUI1510_DSP_STATUS_REG: 0x%-8x \n"
|
|
"MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
|
|
"MPUI1510_DSP_API_CONFIG_REG: 0x%-8x \n"
|
|
"MPUI1510_SDRAM_CONFIG_REG: 0x%-8x \n"
|
|
"MPUI1510_EMIFS_CONFIG_REG: 0x%-8x \n",
|
|
MPUI1510_SHOW(MPUI_CTRL),
|
|
MPUI1510_SHOW(MPUI_DSP_STATUS),
|
|
MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
|
|
MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
|
|
MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
|
|
MPUI1510_SHOW(EMIFS_CONFIG));
|
|
} else if (cpu_is_omap16xx()) {
|
|
my_buffer_offset += sprintf(my_base + my_buffer_offset,
|
|
"MPUI1610_CTRL_REG 0x%-8x \n"
|
|
"MPUI1610_DSP_STATUS_REG: 0x%-8x \n"
|
|
"MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
|
|
"MPUI1610_DSP_API_CONFIG_REG: 0x%-8x \n"
|
|
"MPUI1610_SDRAM_CONFIG_REG: 0x%-8x \n"
|
|
"MPUI1610_EMIFS_CONFIG_REG: 0x%-8x \n",
|
|
MPUI1610_SHOW(MPUI_CTRL),
|
|
MPUI1610_SHOW(MPUI_DSP_STATUS),
|
|
MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
|
|
MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
|
|
MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
|
|
MPUI1610_SHOW(EMIFS_CONFIG));
|
|
}
|
|
|
|
g_read_completed++;
|
|
} else if (g_read_completed >= 1) {
|
|
*eof = 1;
|
|
return 0;
|
|
}
|
|
g_read_completed++;
|
|
|
|
*my_first_byte = page_buffer;
|
|
return my_buffer_offset;
|
|
}
|
|
|
|
static void omap_pm_init_proc(void)
|
|
{
|
|
struct proc_dir_entry *entry;
|
|
|
|
entry = create_proc_read_entry("driver/omap_pm",
|
|
S_IWUSR | S_IRUGO, NULL,
|
|
omap_pm_read_proc, 0);
|
|
}
|
|
|
|
#endif /* DEBUG && CONFIG_PROC_FS */
|
|
|
|
/*
|
|
* omap_pm_prepare - Do preliminary suspend work.
|
|
* @state: suspend state we're entering.
|
|
*
|
|
*/
|
|
//#include <asm/arch/hardware.h>
|
|
|
|
static int omap_pm_prepare(suspend_state_t state)
|
|
{
|
|
int error = 0;
|
|
|
|
switch (state)
|
|
{
|
|
case PM_SUSPEND_STANDBY:
|
|
case PM_SUSPEND_MEM:
|
|
break;
|
|
|
|
case PM_SUSPEND_DISK:
|
|
return -ENOTSUPP;
|
|
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return error;
|
|
}
|
|
|
|
|
|
/*
|
|
* omap_pm_enter - Actually enter a sleep state.
|
|
* @state: State we're entering.
|
|
*
|
|
*/
|
|
|
|
static int omap_pm_enter(suspend_state_t state)
|
|
{
|
|
switch (state)
|
|
{
|
|
case PM_SUSPEND_STANDBY:
|
|
case PM_SUSPEND_MEM:
|
|
omap_pm_suspend();
|
|
break;
|
|
|
|
case PM_SUSPEND_DISK:
|
|
return -ENOTSUPP;
|
|
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
/**
|
|
* omap_pm_finish - Finish up suspend sequence.
|
|
* @state: State we're coming out of.
|
|
*
|
|
* This is called after we wake back up (or if entering the sleep state
|
|
* failed).
|
|
*/
|
|
|
|
static int omap_pm_finish(suspend_state_t state)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
|
|
struct pm_ops omap_pm_ops ={
|
|
.pm_disk_mode = 0,
|
|
.prepare = omap_pm_prepare,
|
|
.enter = omap_pm_enter,
|
|
.finish = omap_pm_finish,
|
|
};
|
|
|
|
static int __init omap_pm_init(void)
|
|
{
|
|
printk("Power Management for TI OMAP.\n");
|
|
pm_idle = omap_pm_idle;
|
|
/*
|
|
* We copy the assembler sleep/wakeup routines to SRAM.
|
|
* These routines need to be in SRAM as that's the only
|
|
* memory the MPU can see when it wakes up.
|
|
*/
|
|
|
|
#ifdef CONFIG_ARCH_OMAP1510
|
|
if (cpu_is_omap1510()) {
|
|
memcpy((void *)OMAP1510_SRAM_IDLE_SUSPEND,
|
|
omap1510_idle_loop_suspend,
|
|
omap1510_idle_loop_suspend_sz);
|
|
memcpy((void *)OMAP1510_SRAM_API_SUSPEND, omap1510_cpu_suspend,
|
|
omap1510_cpu_suspend_sz);
|
|
} else
|
|
#endif
|
|
if (cpu_is_omap1610() || cpu_is_omap1710()) {
|
|
memcpy((void *)OMAP1610_SRAM_IDLE_SUSPEND,
|
|
omap1610_idle_loop_suspend,
|
|
omap1610_idle_loop_suspend_sz);
|
|
memcpy((void *)OMAP1610_SRAM_API_SUSPEND, omap1610_cpu_suspend,
|
|
omap1610_cpu_suspend_sz);
|
|
} else if (cpu_is_omap5912()) {
|
|
memcpy((void *)OMAP5912_SRAM_IDLE_SUSPEND,
|
|
omap1610_idle_loop_suspend,
|
|
omap1610_idle_loop_suspend_sz);
|
|
memcpy((void *)OMAP5912_SRAM_API_SUSPEND, omap1610_cpu_suspend,
|
|
omap1610_cpu_suspend_sz);
|
|
}
|
|
|
|
pm_set_ops(&omap_pm_ops);
|
|
|
|
#if defined(DEBUG) && defined(CONFIG_PROC_FS)
|
|
omap_pm_init_proc();
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
__initcall(omap_pm_init);
|
|
|