forked from Minki/linux
0d900bbbae
Update the copyright period and get rid of some spurious newlines. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2082 lines
57 KiB
Plaintext
2082 lines
57 KiB
Plaintext
/*
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* Copyright 2016-2018 Toradex AG
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "tegra124.dtsi"
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#include "tegra124-apalis-emc.dtsi"
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/*
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* Toradex Apalis TK1 Module Device Tree
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* Compatible for Revisions 2GB: V1.0A, V1.0B, V1.1A
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*/
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/ {
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model = "Toradex Apalis TK1";
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compatible = "toradex,apalis-tk1", "nvidia,tegra124";
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memory {
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reg = <0x0 0x80000000 0x0 0x80000000>;
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};
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pcie@1003000 {
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status = "okay";
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avddio-pex-supply = <&vdd_1v05>;
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avdd-pex-pll-supply = <&vdd_1v05>;
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avdd-pll-erefe-supply = <&avdd_1v05>;
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dvddio-pex-supply = <&vdd_1v05>;
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hvdd-pex-pll-e-supply = <®_3v3>;
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hvdd-pex-supply = <®_3v3>;
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vddio-pex-ctl-supply = <®_3v3>;
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/* Apalis PCIe (additional lane Apalis type specific) */
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pci@1,0 {
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/* PCIE1_RX/TX and TS_DIFF1/2 */
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phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>,
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<&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
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phy-names = "pcie-0", "pcie-1";
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};
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/* I210 Gigabit Ethernet Controller (On-module) */
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pci@2,0 {
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phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
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phy-names = "pcie-0";
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status = "okay";
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};
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};
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host1x@50000000 {
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hdmi@54280000 {
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pll-supply = <®_1v05_avdd_hdmi_pll>;
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vdd-supply = <®_3v3_avdd_hdmi>;
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nvidia,ddc-i2c-bus = <&hdmi_ddc>;
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nvidia,hpd-gpio =
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<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
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};
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};
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gpu@0,57000000 {
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/*
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* Node left disabled on purpose - the bootloader will enable
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* it after having set the VPR up
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*/
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vdd-supply = <&vdd_gpu>;
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};
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pinmux: pinmux@70000868 {
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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state_default: pinmux {
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/* Analogue Audio (On-module) */
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dap3_fs_pp0 {
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nvidia,pins = "dap3_fs_pp0";
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nvidia,function = "i2s2";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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dap3_din_pp1 {
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nvidia,pins = "dap3_din_pp1";
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nvidia,function = "i2s2";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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dap3_dout_pp2 {
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nvidia,pins = "dap3_dout_pp2";
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nvidia,function = "i2s2";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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dap3_sclk_pp3 {
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nvidia,pins = "dap3_sclk_pp3";
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nvidia,function = "i2s2";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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dap_mclk1_pw4 {
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nvidia,pins = "dap_mclk1_pw4";
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nvidia,function = "extperiph1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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/* Apalis BKL1_ON */
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pbb5 {
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nvidia,pins = "pbb5";
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nvidia,function = "vgp5";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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/* Apalis BKL1_PWM */
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pu6 {
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nvidia,pins = "pu6";
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nvidia,function = "pwm3";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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/* Apalis CAM1_MCLK */
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cam_mclk_pcc0 {
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nvidia,pins = "cam_mclk_pcc0";
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nvidia,function = "vi_alt3";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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/* Apalis Digital Audio */
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dap2_fs_pa2 {
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nvidia,pins = "dap2_fs_pa2";
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nvidia,function = "hda";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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dap2_sclk_pa3 {
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nvidia,pins = "dap2_sclk_pa3";
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nvidia,function = "hda";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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dap2_din_pa4 {
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nvidia,pins = "dap2_din_pa4";
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nvidia,function = "hda";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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dap2_dout_pa5 {
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nvidia,pins = "dap2_dout_pa5";
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nvidia,function = "hda";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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pbb3 { /* DAP1_RESET */
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nvidia,pins = "pbb3";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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clk3_out_pee0 {
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nvidia,pins = "clk3_out_pee0";
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nvidia,function = "extperiph3";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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/* Apalis GPIO */
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ddc_scl_pv4 {
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nvidia,pins = "ddc_scl_pv4";
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nvidia,function = "rsvd2";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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ddc_sda_pv5 {
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nvidia,pins = "ddc_sda_pv5";
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nvidia,function = "rsvd2";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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pex_l0_rst_n_pdd1 {
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nvidia,pins = "pex_l0_rst_n_pdd1";
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nvidia,function = "rsvd2";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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pex_l0_clkreq_n_pdd2 {
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nvidia,pins = "pex_l0_clkreq_n_pdd2";
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nvidia,function = "rsvd2";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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pex_l1_rst_n_pdd5 {
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nvidia,pins = "pex_l1_rst_n_pdd5";
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nvidia,function = "rsvd2";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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pex_l1_clkreq_n_pdd6 {
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nvidia,pins = "pex_l1_clkreq_n_pdd6";
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nvidia,function = "rsvd2";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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dp_hpd_pff0 {
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nvidia,pins = "dp_hpd_pff0";
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nvidia,function = "dp";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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pff2 {
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nvidia,pins = "pff2";
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nvidia,function = "rsvd2";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */
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nvidia,pins = "owr";
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nvidia,function = "rsvd2";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
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};
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/* Apalis HDMI1_CEC */
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hdmi_cec_pee3 {
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nvidia,pins = "hdmi_cec_pee3";
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nvidia,function = "cec";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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/* Apalis HDMI1_HPD */
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hdmi_int_pn7 {
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nvidia,pins = "hdmi_int_pn7";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
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};
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/* Apalis I2C1 */
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gen1_i2c_scl_pc4 {
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nvidia,pins = "gen1_i2c_scl_pc4";
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nvidia,function = "i2c1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_ENABLE>;
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};
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gen1_i2c_sda_pc5 {
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nvidia,pins = "gen1_i2c_sda_pc5";
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nvidia,function = "i2c1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_ENABLE>;
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};
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/* Apalis I2C2 (DDC) */
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gen2_i2c_scl_pt5 {
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nvidia,pins = "gen2_i2c_scl_pt5";
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nvidia,function = "i2c2";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_ENABLE>;
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};
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gen2_i2c_sda_pt6 {
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nvidia,pins = "gen2_i2c_sda_pt6";
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nvidia,function = "i2c2";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_ENABLE>;
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};
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/* Apalis I2C3 (CAM) */
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cam_i2c_scl_pbb1 {
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nvidia,pins = "cam_i2c_scl_pbb1";
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nvidia,function = "i2c3";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_ENABLE>;
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};
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cam_i2c_sda_pbb2 {
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nvidia,pins = "cam_i2c_sda_pbb2";
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nvidia,function = "i2c3";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_ENABLE>;
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};
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/* Apalis MMC1 */
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sdmmc1_cd_n_pv3 { /* CD# GPIO */
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nvidia,pins = "sdmmc1_wp_n_pv3";
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nvidia,function = "sdmmc1";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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clk2_out_pw5 { /* D5 GPIO */
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nvidia,pins = "clk2_out_pw5";
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nvidia,function = "rsvd2";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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sdmmc1_dat3_py4 {
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nvidia,pins = "sdmmc1_dat3_py4";
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nvidia,function = "sdmmc1";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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sdmmc1_dat2_py5 {
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nvidia,pins = "sdmmc1_dat2_py5";
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nvidia,function = "sdmmc1";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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sdmmc1_dat1_py6 {
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nvidia,pins = "sdmmc1_dat1_py6";
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nvidia,function = "sdmmc1";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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sdmmc1_dat0_py7 {
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nvidia,pins = "sdmmc1_dat0_py7";
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nvidia,function = "sdmmc1";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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sdmmc1_clk_pz0 {
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nvidia,pins = "sdmmc1_clk_pz0";
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nvidia,function = "sdmmc1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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sdmmc1_cmd_pz1 {
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nvidia,pins = "sdmmc1_cmd_pz1";
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nvidia,function = "sdmmc1";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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clk2_req_pcc5 { /* D4 GPIO */
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nvidia,pins = "clk2_req_pcc5";
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nvidia,function = "rsvd2";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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sdmmc3_clk_lb_in_pee5 { /* D6 GPIO */
|
|
nvidia,pins = "sdmmc3_clk_lb_in_pee5";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
usb_vbus_en2_pff1 { /* D7 GPIO */
|
|
nvidia,pins = "usb_vbus_en2_pff1";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* Apalis PWM */
|
|
ph0 {
|
|
nvidia,pins = "ph0";
|
|
nvidia,function = "pwm0";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ph1 {
|
|
nvidia,pins = "ph1";
|
|
nvidia,function = "pwm1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ph2 {
|
|
nvidia,pins = "ph2";
|
|
nvidia,function = "pwm2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
/* PWM3 active on pu6 being Apalis BKL1_PWM as well */
|
|
ph3 {
|
|
nvidia,pins = "ph3";
|
|
nvidia,function = "pwm3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* Apalis SATA1_ACT# */
|
|
dap1_dout_pn2 {
|
|
nvidia,pins = "dap1_dout_pn2";
|
|
nvidia,function = "gmi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* Apalis SD1 */
|
|
sdmmc3_clk_pa6 {
|
|
nvidia,pins = "sdmmc3_clk_pa6";
|
|
nvidia,function = "sdmmc3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc3_cmd_pa7 {
|
|
nvidia,pins = "sdmmc3_cmd_pa7";
|
|
nvidia,function = "sdmmc3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc3_dat3_pb4 {
|
|
nvidia,pins = "sdmmc3_dat3_pb4";
|
|
nvidia,function = "sdmmc3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc3_dat2_pb5 {
|
|
nvidia,pins = "sdmmc3_dat2_pb5";
|
|
nvidia,function = "sdmmc3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc3_dat1_pb6 {
|
|
nvidia,pins = "sdmmc3_dat1_pb6";
|
|
nvidia,function = "sdmmc3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc3_dat0_pb7 {
|
|
nvidia,pins = "sdmmc3_dat0_pb7";
|
|
nvidia,function = "sdmmc3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc3_cd_n_pv2 { /* CD# GPIO */
|
|
nvidia,pins = "sdmmc3_cd_n_pv2";
|
|
nvidia,function = "rsvd3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* Apalis SPDIF */
|
|
spdif_out_pk5 {
|
|
nvidia,pins = "spdif_out_pk5";
|
|
nvidia,function = "spdif";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
spdif_in_pk6 {
|
|
nvidia,pins = "spdif_in_pk6";
|
|
nvidia,function = "spdif";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* Apalis SPI1 */
|
|
ulpi_clk_py0 {
|
|
nvidia,pins = "ulpi_clk_py0";
|
|
nvidia,function = "spi1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ulpi_dir_py1 {
|
|
nvidia,pins = "ulpi_dir_py1";
|
|
nvidia,function = "spi1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
ulpi_nxt_py2 {
|
|
nvidia,pins = "ulpi_nxt_py2";
|
|
nvidia,function = "spi1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ulpi_stp_py3 {
|
|
nvidia,pins = "ulpi_stp_py3";
|
|
nvidia,function = "spi1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* Apalis SPI2 */
|
|
pg5 {
|
|
nvidia,pins = "pg5";
|
|
nvidia,function = "spi4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pg6 {
|
|
nvidia,pins = "pg6";
|
|
nvidia,function = "spi4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pg7 {
|
|
nvidia,pins = "pg7";
|
|
nvidia,function = "spi4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pi3 {
|
|
nvidia,pins = "pi3";
|
|
nvidia,function = "spi4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* Apalis UART1 */
|
|
pb1 { /* DCD GPIO */
|
|
nvidia,pins = "pb1";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pk7 { /* RI GPIO */
|
|
nvidia,pins = "pk7";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
uart1_txd_pu0 {
|
|
nvidia,pins = "pu0";
|
|
nvidia,function = "uarta";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
uart1_rxd_pu1 {
|
|
nvidia,pins = "pu1";
|
|
nvidia,function = "uarta";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
uart1_cts_n_pu2 {
|
|
nvidia,pins = "pu2";
|
|
nvidia,function = "uarta";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
uart1_rts_n_pu3 {
|
|
nvidia,pins = "pu3";
|
|
nvidia,function = "uarta";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
uart3_cts_n_pa1 { /* DSR GPIO */
|
|
nvidia,pins = "uart3_cts_n_pa1";
|
|
nvidia,function = "gmi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
uart3_rts_n_pc0 { /* DTR GPIO */
|
|
nvidia,pins = "uart3_rts_n_pc0";
|
|
nvidia,function = "gmi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* Apalis UART2 */
|
|
uart2_txd_pc2 {
|
|
nvidia,pins = "uart2_txd_pc2";
|
|
nvidia,function = "irda";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
uart2_rxd_pc3 {
|
|
nvidia,pins = "uart2_rxd_pc3";
|
|
nvidia,function = "irda";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
uart2_cts_n_pj5 {
|
|
nvidia,pins = "uart2_cts_n_pj5";
|
|
nvidia,function = "uartb";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
uart2_rts_n_pj6 {
|
|
nvidia,pins = "uart2_rts_n_pj6";
|
|
nvidia,function = "uartb";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* Apalis UART3 */
|
|
uart3_txd_pw6 {
|
|
nvidia,pins = "uart3_txd_pw6";
|
|
nvidia,function = "uartc";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
uart3_rxd_pw7 {
|
|
nvidia,pins = "uart3_rxd_pw7";
|
|
nvidia,function = "uartc";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* Apalis UART4 */
|
|
uart4_rxd_pb0 {
|
|
nvidia,pins = "pb0";
|
|
nvidia,function = "uartd";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
uart4_txd_pj7 {
|
|
nvidia,pins = "pj7";
|
|
nvidia,function = "uartd";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* Apalis USBH_EN */
|
|
usb_vbus_en1_pn5 {
|
|
nvidia,pins = "usb_vbus_en1_pn5";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* Apalis USBH_OC# */
|
|
pbb0 {
|
|
nvidia,pins = "pbb0";
|
|
nvidia,function = "vgp6";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* Apalis USBO1_EN */
|
|
usb_vbus_en0_pn4 {
|
|
nvidia,pins = "usb_vbus_en0_pn4";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* Apalis USBO1_OC# */
|
|
pbb4 {
|
|
nvidia,pins = "pbb4";
|
|
nvidia,function = "vgp4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* Apalis WAKE1_MICO */
|
|
pex_wake_n_pdd3 {
|
|
nvidia,pins = "pex_wake_n_pdd3";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* CORE_PWR_REQ */
|
|
core_pwr_req {
|
|
nvidia,pins = "core_pwr_req";
|
|
nvidia,function = "pwron";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* CPU_PWR_REQ */
|
|
cpu_pwr_req {
|
|
nvidia,pins = "cpu_pwr_req";
|
|
nvidia,function = "cpu";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* DVFS */
|
|
dvfs_pwm_px0 {
|
|
nvidia,pins = "dvfs_pwm_px0";
|
|
nvidia,function = "cldvfs";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dvfs_clk_px2 {
|
|
nvidia,pins = "dvfs_clk_px2";
|
|
nvidia,function = "cldvfs";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* eMMC */
|
|
sdmmc4_dat0_paa0 {
|
|
nvidia,pins = "sdmmc4_dat0_paa0";
|
|
nvidia,function = "sdmmc4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc4_dat1_paa1 {
|
|
nvidia,pins = "sdmmc4_dat1_paa1";
|
|
nvidia,function = "sdmmc4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc4_dat2_paa2 {
|
|
nvidia,pins = "sdmmc4_dat2_paa2";
|
|
nvidia,function = "sdmmc4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc4_dat3_paa3 {
|
|
nvidia,pins = "sdmmc4_dat3_paa3";
|
|
nvidia,function = "sdmmc4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc4_dat4_paa4 {
|
|
nvidia,pins = "sdmmc4_dat4_paa4";
|
|
nvidia,function = "sdmmc4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc4_dat5_paa5 {
|
|
nvidia,pins = "sdmmc4_dat5_paa5";
|
|
nvidia,function = "sdmmc4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc4_dat6_paa6 {
|
|
nvidia,pins = "sdmmc4_dat6_paa6";
|
|
nvidia,function = "sdmmc4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc4_dat7_paa7 {
|
|
nvidia,pins = "sdmmc4_dat7_paa7";
|
|
nvidia,function = "sdmmc4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc4_clk_pcc4 {
|
|
nvidia,pins = "sdmmc4_clk_pcc4";
|
|
nvidia,function = "sdmmc4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc4_cmd_pt7 {
|
|
nvidia,pins = "sdmmc4_cmd_pt7";
|
|
nvidia,function = "sdmmc4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* JTAG_RTCK */
|
|
jtag_rtck {
|
|
nvidia,pins = "jtag_rtck";
|
|
nvidia,function = "rtck";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* LAN_DEV_OFF# */
|
|
ulpi_data5_po6 {
|
|
nvidia,pins = "ulpi_data5_po6";
|
|
nvidia,function = "ulpi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* LAN_RESET# */
|
|
kb_row10_ps2 {
|
|
nvidia,pins = "kb_row10_ps2";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* LAN_WAKE# */
|
|
ulpi_data4_po5 {
|
|
nvidia,pins = "ulpi_data4_po5";
|
|
nvidia,function = "ulpi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* MCU_INT1# */
|
|
pk2 {
|
|
nvidia,pins = "pk2";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* MCU_INT2# */
|
|
pj2 {
|
|
nvidia,pins = "pj2";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* MCU_INT3# */
|
|
pi5 {
|
|
nvidia,pins = "pi5";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* MCU_INT4# */
|
|
pj0 {
|
|
nvidia,pins = "pj0";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* MCU_RESET */
|
|
pbb6 {
|
|
nvidia,pins = "pbb6";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* MCU SPI */
|
|
gpio_x4_aud_px4 {
|
|
nvidia,pins = "gpio_x4_aud_px4";
|
|
nvidia,function = "spi2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
gpio_x5_aud_px5 {
|
|
nvidia,pins = "gpio_x5_aud_px5";
|
|
nvidia,function = "spi2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
gpio_x6_aud_px6 { /* MCU_CS */
|
|
nvidia,pins = "gpio_x6_aud_px6";
|
|
nvidia,function = "spi2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
gpio_x7_aud_px7 {
|
|
nvidia,pins = "gpio_x7_aud_px7";
|
|
nvidia,function = "spi2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
gpio_w2_aud_pw2 { /* MCU_CSEZP */
|
|
nvidia,pins = "gpio_w2_aud_pw2";
|
|
nvidia,function = "spi2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* PMIC_CLK_32K */
|
|
clk_32k_in {
|
|
nvidia,pins = "clk_32k_in";
|
|
nvidia,function = "clk";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* PMIC_CPU_OC_INT */
|
|
clk_32k_out_pa0 {
|
|
nvidia,pins = "clk_32k_out_pa0";
|
|
nvidia,function = "soc";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* PWR_I2C */
|
|
pwr_i2c_scl_pz6 {
|
|
nvidia,pins = "pwr_i2c_scl_pz6";
|
|
nvidia,function = "i2cpwr";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pwr_i2c_sda_pz7 {
|
|
nvidia,pins = "pwr_i2c_sda_pz7";
|
|
nvidia,function = "i2cpwr";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* PWR_INT_N */
|
|
pwr_int_n {
|
|
nvidia,pins = "pwr_int_n";
|
|
nvidia,function = "pmi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* RESET_MOCI_CTRL */
|
|
pu4 {
|
|
nvidia,pins = "pu4";
|
|
nvidia,function = "gmi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* RESET_OUT_N */
|
|
reset_out_n {
|
|
nvidia,pins = "reset_out_n";
|
|
nvidia,function = "reset_out_n";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* SHIFT_CTRL_DIR_IN */
|
|
kb_row0_pr0 {
|
|
nvidia,pins = "kb_row0_pr0";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_row1_pr1 {
|
|
nvidia,pins = "kb_row1_pr1";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* Configure level-shifter as output for HDA */
|
|
kb_row11_ps3 {
|
|
nvidia,pins = "kb_row11_ps3";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* SHIFT_CTRL_DIR_OUT */
|
|
kb_col5_pq5 {
|
|
nvidia,pins = "kb_col5_pq5";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_col6_pq6 {
|
|
nvidia,pins = "kb_col6_pq6";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_col7_pq7 {
|
|
nvidia,pins = "kb_col7_pq7";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* SHIFT_CTRL_OE */
|
|
kb_col0_pq0 {
|
|
nvidia,pins = "kb_col0_pq0";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_col1_pq1 {
|
|
nvidia,pins = "kb_col1_pq1";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_col2_pq2 {
|
|
nvidia,pins = "kb_col2_pq2";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_col4_pq4 {
|
|
nvidia,pins = "kb_col4_pq4";
|
|
nvidia,function = "kbc";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_row2_pr2 {
|
|
nvidia,pins = "kb_row2_pr2";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* GPIO_PI6 aka TMP451 ALERT#/THERM2# */
|
|
pi6 {
|
|
nvidia,pins = "pi6";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* TOUCH_INT */
|
|
gpio_w3_aud_pw3 {
|
|
nvidia,pins = "gpio_w3_aud_pw3";
|
|
nvidia,function = "spi6";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
pc7 { /* NC */
|
|
nvidia,pins = "pc7";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pg0 { /* NC */
|
|
nvidia,pins = "pg0";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pg1 { /* NC */
|
|
nvidia,pins = "pg1";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pg2 { /* NC */
|
|
nvidia,pins = "pg2";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pg3 { /* NC */
|
|
nvidia,pins = "pg3";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pg4 { /* NC */
|
|
nvidia,pins = "pg4";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ph4 { /* NC */
|
|
nvidia,pins = "ph4";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ph5 { /* NC */
|
|
nvidia,pins = "ph5";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ph6 { /* NC */
|
|
nvidia,pins = "ph6";
|
|
nvidia,function = "gmi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ph7 { /* NC */
|
|
nvidia,pins = "ph7";
|
|
nvidia,function = "gmi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pi0 { /* NC */
|
|
nvidia,pins = "pi0";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pi1 { /* NC */
|
|
nvidia,pins = "pi1";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pi2 { /* NC */
|
|
nvidia,pins = "pi2";
|
|
nvidia,function = "rsvd4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pi4 { /* NC */
|
|
nvidia,pins = "pi4";
|
|
nvidia,function = "gmi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pi7 { /* NC */
|
|
nvidia,pins = "pi7";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pk0 { /* NC */
|
|
nvidia,pins = "pk0";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pk1 { /* NC */
|
|
nvidia,pins = "pk1";
|
|
nvidia,function = "rsvd4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pk3 { /* NC */
|
|
nvidia,pins = "pk3";
|
|
nvidia,function = "gmi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pk4 { /* NC */
|
|
nvidia,pins = "pk4";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap1_fs_pn0 { /* NC */
|
|
nvidia,pins = "dap1_fs_pn0";
|
|
nvidia,function = "rsvd4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap1_din_pn1 { /* NC */
|
|
nvidia,pins = "dap1_din_pn1";
|
|
nvidia,function = "rsvd4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap1_sclk_pn3 { /* NC */
|
|
nvidia,pins = "dap1_sclk_pn3";
|
|
nvidia,function = "rsvd4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ulpi_data7_po0 { /* NC */
|
|
nvidia,pins = "ulpi_data7_po0";
|
|
nvidia,function = "ulpi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ulpi_data0_po1 { /* NC */
|
|
nvidia,pins = "ulpi_data0_po1";
|
|
nvidia,function = "ulpi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ulpi_data1_po2 { /* NC */
|
|
nvidia,pins = "ulpi_data1_po2";
|
|
nvidia,function = "ulpi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ulpi_data2_po3 { /* NC */
|
|
nvidia,pins = "ulpi_data2_po3";
|
|
nvidia,function = "ulpi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ulpi_data3_po4 { /* NC */
|
|
nvidia,pins = "ulpi_data3_po4";
|
|
nvidia,function = "ulpi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ulpi_data6_po7 { /* NC */
|
|
nvidia,pins = "ulpi_data6_po7";
|
|
nvidia,function = "ulpi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap4_fs_pp4 { /* NC */
|
|
nvidia,pins = "dap4_fs_pp4";
|
|
nvidia,function = "rsvd4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap4_din_pp5 { /* NC */
|
|
nvidia,pins = "dap4_din_pp5";
|
|
nvidia,function = "rsvd3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap4_dout_pp6 { /* NC */
|
|
nvidia,pins = "dap4_dout_pp6";
|
|
nvidia,function = "rsvd4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap4_sclk_pp7 { /* NC */
|
|
nvidia,pins = "dap4_sclk_pp7";
|
|
nvidia,function = "rsvd3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_col3_pq3 { /* NC */
|
|
nvidia,pins = "kb_col3_pq3";
|
|
nvidia,function = "kbc";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_row3_pr3 { /* NC */
|
|
nvidia,pins = "kb_row3_pr3";
|
|
nvidia,function = "kbc";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_row4_pr4 { /* NC */
|
|
nvidia,pins = "kb_row4_pr4";
|
|
nvidia,function = "rsvd3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_row5_pr5 { /* NC */
|
|
nvidia,pins = "kb_row5_pr5";
|
|
nvidia,function = "rsvd3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_row6_pr6 { /* NC */
|
|
nvidia,pins = "kb_row6_pr6";
|
|
nvidia,function = "kbc";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_row7_pr7 { /* NC */
|
|
nvidia,pins = "kb_row7_pr7";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_row8_ps0 { /* NC */
|
|
nvidia,pins = "kb_row8_ps0";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_row9_ps1 { /* NC */
|
|
nvidia,pins = "kb_row9_ps1";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_row12_ps4 { /* NC */
|
|
nvidia,pins = "kb_row12_ps4";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_row13_ps5 { /* NC */
|
|
nvidia,pins = "kb_row13_ps5";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_row14_ps6 { /* NC */
|
|
nvidia,pins = "kb_row14_ps6";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_row15_ps7 { /* NC */
|
|
nvidia,pins = "kb_row15_ps7";
|
|
nvidia,function = "rsvd3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_row16_pt0 { /* NC */
|
|
nvidia,pins = "kb_row16_pt0";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_row17_pt1 { /* NC */
|
|
nvidia,pins = "kb_row17_pt1";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pu5 { /* NC */
|
|
nvidia,pins = "pu5";
|
|
nvidia,function = "gmi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pv0 { /* NC */
|
|
nvidia,pins = "pv0";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pv1 { /* NC */
|
|
nvidia,pins = "pv1";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
gpio_x1_aud_px1 { /* NC */
|
|
nvidia,pins = "gpio_x1_aud_px1";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
gpio_x3_aud_px3 { /* NC */
|
|
nvidia,pins = "gpio_x3_aud_px3";
|
|
nvidia,function = "rsvd4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pbb7 { /* NC */
|
|
nvidia,pins = "pbb7";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pcc1 { /* NC */
|
|
nvidia,pins = "pcc1";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pcc2 { /* NC */
|
|
nvidia,pins = "pcc2";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
clk3_req_pee1 { /* NC */
|
|
nvidia,pins = "clk3_req_pee1";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap_mclk1_req_pee2 { /* NC */
|
|
nvidia,pins = "dap_mclk1_req_pee2";
|
|
nvidia,function = "rsvd4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
/*
|
|
* Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output
|
|
* driver enabled aka not tristated and input driver
|
|
* enabled as well as it features some magic properties
|
|
* even though the external loopback is disabled and the
|
|
* internal loopback used as per
|
|
* SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
|
|
* bits being set to 0xfffd according to the TRM!
|
|
*/
|
|
sdmmc3_clk_lb_out_pee4 { /* NC */
|
|
nvidia,pins = "sdmmc3_clk_lb_out_pee4";
|
|
nvidia,function = "sdmmc3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
};
|
|
};
|
|
|
|
serial@70006040 {
|
|
compatible = "nvidia,tegra124-hsuart";
|
|
};
|
|
|
|
serial@70006200 {
|
|
compatible = "nvidia,tegra124-hsuart";
|
|
};
|
|
|
|
serial@70006300 {
|
|
compatible = "nvidia,tegra124-hsuart";
|
|
};
|
|
|
|
hdmi_ddc: i2c@7000c400 {
|
|
clock-frequency = <10000>;
|
|
};
|
|
|
|
/* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */
|
|
i2c@7000d000 {
|
|
status = "okay";
|
|
clock-frequency = <400000>;
|
|
|
|
/* SGTL5000 audio codec */
|
|
sgtl5000: codec@a {
|
|
compatible = "fsl,sgtl5000";
|
|
reg = <0x0a>;
|
|
VDDA-supply = <®_3v3>;
|
|
VDDIO-supply = <&vddio_1v8>;
|
|
clocks = <&tegra_car TEGRA124_CLK_EXTERN1>;
|
|
};
|
|
|
|
pmic: pmic@40 {
|
|
compatible = "ams,as3722";
|
|
reg = <0x40>;
|
|
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
ams,system-power-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&as3722_default>;
|
|
|
|
as3722_default: pinmux {
|
|
gpio2_7 {
|
|
pins = "gpio2", /* PWR_EN_+V3.3 */
|
|
"gpio7"; /* +V1.6_LPO */
|
|
function = "gpio";
|
|
bias-pull-up;
|
|
};
|
|
|
|
gpio0_1_3_4_5_6 {
|
|
pins = "gpio0", "gpio1", "gpio3",
|
|
"gpio4", "gpio5", "gpio6";
|
|
bias-high-impedance;
|
|
};
|
|
};
|
|
|
|
regulators {
|
|
vsup-sd2-supply = <®_3v3>;
|
|
vsup-sd3-supply = <®_3v3>;
|
|
vsup-sd4-supply = <®_3v3>;
|
|
vsup-sd5-supply = <®_3v3>;
|
|
vin-ldo0-supply = <&vddio_ddr_1v35>;
|
|
vin-ldo1-6-supply = <®_3v3>;
|
|
vin-ldo2-5-7-supply = <&vddio_1v8>;
|
|
vin-ldo3-4-supply = <®_3v3>;
|
|
vin-ldo9-10-supply = <®_3v3>;
|
|
vin-ldo11-supply = <®_3v3>;
|
|
|
|
vdd_cpu: sd0 {
|
|
regulator-name = "+VDD_CPU_AP";
|
|
regulator-min-microvolt = <700000>;
|
|
regulator-max-microvolt = <1400000>;
|
|
regulator-min-microamp = <3500000>;
|
|
regulator-max-microamp = <3500000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
ams,ext-control = <2>;
|
|
};
|
|
|
|
sd1 {
|
|
regulator-name = "+VDD_CORE";
|
|
regulator-min-microvolt = <700000>;
|
|
regulator-max-microvolt = <1350000>;
|
|
regulator-min-microamp = <2500000>;
|
|
regulator-max-microamp = <4000000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
ams,ext-control = <1>;
|
|
};
|
|
|
|
vddio_ddr_1v35: sd2 {
|
|
regulator-name =
|
|
"+V1.35_VDDIO_DDR(sd2)";
|
|
regulator-min-microvolt = <1350000>;
|
|
regulator-max-microvolt = <1350000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
sd3 {
|
|
regulator-name =
|
|
"+V1.35_VDDIO_DDR(sd3)";
|
|
regulator-min-microvolt = <1350000>;
|
|
regulator-max-microvolt = <1350000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
vdd_1v05: sd4 {
|
|
regulator-name = "+V1.05";
|
|
regulator-min-microvolt = <1050000>;
|
|
regulator-max-microvolt = <1050000>;
|
|
};
|
|
|
|
vddio_1v8: sd5 {
|
|
regulator-name = "+V1.8";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
vdd_gpu: sd6 {
|
|
regulator-name = "+VDD_GPU_AP";
|
|
regulator-min-microvolt = <650000>;
|
|
regulator-max-microvolt = <1200000>;
|
|
regulator-min-microamp = <3500000>;
|
|
regulator-max-microamp = <3500000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
avdd_1v05: ldo0 {
|
|
regulator-name = "+V1.05_AVDD";
|
|
regulator-min-microvolt = <1050000>;
|
|
regulator-max-microvolt = <1050000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
ams,ext-control = <1>;
|
|
};
|
|
|
|
vddio_sdmmc1: ldo1 {
|
|
regulator-name = "VDDIO_SDMMC1";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
};
|
|
|
|
ldo2 {
|
|
regulator-name = "+V1.2";
|
|
regulator-min-microvolt = <1200000>;
|
|
regulator-max-microvolt = <1200000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo3 {
|
|
regulator-name = "+V1.05_RTC";
|
|
regulator-min-microvolt = <1000000>;
|
|
regulator-max-microvolt = <1000000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
ams,enable-tracking;
|
|
};
|
|
|
|
/* 1.8V for LVDS, 3.3V for eDP */
|
|
ldo4 {
|
|
regulator-name = "AVDD_LVDS0_PLL";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
};
|
|
|
|
/* LDO5 not used */
|
|
|
|
vddio_sdmmc3: ldo6 {
|
|
regulator-name = "VDDIO_SDMMC3";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
};
|
|
|
|
/* LDO7 not used */
|
|
|
|
ldo9 {
|
|
regulator-name = "+V3.3_ETH(ldo9)";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo10 {
|
|
regulator-name = "+V3.3_ETH(ldo10)";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo11 {
|
|
regulator-name = "+V1.8_VPP_FUSE";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
/*
|
|
* TMP451 temperature sensor
|
|
* Note: THERM_N directly connected to AS3722 PMIC THERM
|
|
*/
|
|
temperature-sensor@4c {
|
|
compatible = "ti,tmp451";
|
|
reg = <0x4c>;
|
|
interrupt-parent = <&gpio>;
|
|
interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
};
|
|
|
|
/* SPI2: MCU SPI */
|
|
spi@7000d600 {
|
|
status = "okay";
|
|
spi-max-frequency = <25000000>;
|
|
};
|
|
|
|
pmc@7000e400 {
|
|
nvidia,invert-interrupt;
|
|
nvidia,suspend-mode = <1>;
|
|
nvidia,cpu-pwr-good-time = <500>;
|
|
nvidia,cpu-pwr-off-time = <300>;
|
|
nvidia,core-pwr-good-time = <641 3845>;
|
|
nvidia,core-pwr-off-time = <61036>;
|
|
nvidia,core-power-req-active-high;
|
|
nvidia,sys-clock-req-active-high;
|
|
|
|
/* Set power_off bit in ResetControl register of AS3722 PMIC */
|
|
i2c-thermtrip {
|
|
nvidia,i2c-controller-id = <4>;
|
|
nvidia,bus-addr = <0x40>;
|
|
nvidia,reg-addr = <0x36>;
|
|
nvidia,reg-data = <0x2>;
|
|
};
|
|
};
|
|
|
|
sata@70020000 {
|
|
phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
|
|
phy-names = "sata-0";
|
|
avdd-supply = <&vdd_1v05>;
|
|
hvdd-supply = <®_3v3>;
|
|
vddio-supply = <&vdd_1v05>;
|
|
};
|
|
|
|
usb@70090000 {
|
|
/* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */
|
|
phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
|
|
<&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
|
|
<&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
|
|
<&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
|
|
<&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
|
|
phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0";
|
|
avddio-pex-supply = <&vdd_1v05>;
|
|
avdd-pll-erefe-supply = <&avdd_1v05>;
|
|
avdd-pll-utmip-supply = <&vddio_1v8>;
|
|
avdd-usb-ss-pll-supply = <&vdd_1v05>;
|
|
avdd-usb-supply = <®_3v3>;
|
|
dvddio-pex-supply = <&vdd_1v05>;
|
|
hvdd-usb-ss-pll-e-supply = <®_3v3>;
|
|
hvdd-usb-ss-supply = <®_3v3>;
|
|
};
|
|
|
|
padctl@7009f000 {
|
|
pads {
|
|
usb2 {
|
|
status = "okay";
|
|
|
|
lanes {
|
|
usb2-0 {
|
|
nvidia,function = "xusb";
|
|
status = "okay";
|
|
};
|
|
|
|
usb2-1 {
|
|
nvidia,function = "xusb";
|
|
status = "okay";
|
|
};
|
|
|
|
usb2-2 {
|
|
nvidia,function = "xusb";
|
|
status = "okay";
|
|
};
|
|
};
|
|
};
|
|
|
|
pcie {
|
|
status = "okay";
|
|
|
|
lanes {
|
|
pcie-0 {
|
|
nvidia,function = "usb3-ss";
|
|
status = "okay";
|
|
};
|
|
|
|
pcie-1 {
|
|
nvidia,function = "usb3-ss";
|
|
status = "okay";
|
|
};
|
|
|
|
pcie-2 {
|
|
nvidia,function = "pcie";
|
|
status = "okay";
|
|
};
|
|
|
|
pcie-3 {
|
|
nvidia,function = "pcie";
|
|
status = "okay";
|
|
};
|
|
|
|
pcie-4 {
|
|
nvidia,function = "pcie";
|
|
status = "okay";
|
|
};
|
|
};
|
|
};
|
|
|
|
sata {
|
|
status = "okay";
|
|
|
|
lanes {
|
|
sata-0 {
|
|
nvidia,function = "sata";
|
|
status = "okay";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ports {
|
|
/* USBO1 */
|
|
usb2-0 {
|
|
status = "okay";
|
|
mode = "otg";
|
|
|
|
vbus-supply = <®_usbo1_vbus>;
|
|
};
|
|
|
|
/* USBH2 */
|
|
usb2-1 {
|
|
status = "okay";
|
|
mode = "host";
|
|
|
|
vbus-supply = <®_usbh_vbus>;
|
|
};
|
|
|
|
/* USBH4 */
|
|
usb2-2 {
|
|
status = "okay";
|
|
mode = "host";
|
|
|
|
vbus-supply = <®_usbh_vbus>;
|
|
};
|
|
|
|
usb3-0 {
|
|
nvidia,usb2-companion = <2>;
|
|
status = "okay";
|
|
};
|
|
|
|
usb3-1 {
|
|
nvidia,usb2-companion = <0>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
};
|
|
|
|
/* eMMC */
|
|
sdhci@700b0600 {
|
|
status = "okay";
|
|
bus-width = <8>;
|
|
non-removable;
|
|
};
|
|
|
|
/* CPU DFLL clock */
|
|
clock@70110000 {
|
|
status = "okay";
|
|
vdd-cpu-supply = <&vdd_cpu>;
|
|
nvidia,i2c-fs-rate = <400000>;
|
|
};
|
|
|
|
ahub@70300000 {
|
|
i2s@70301200 {
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
clocks {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
clk32k_in: clock@0 {
|
|
compatible = "fixed-clock";
|
|
reg = <0>;
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32768>;
|
|
};
|
|
};
|
|
|
|
cpus {
|
|
cpu@0 {
|
|
vdd-cpu-supply = <&vdd_cpu>;
|
|
};
|
|
};
|
|
|
|
reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "+V1.05_AVDD_HDMI_PLL";
|
|
regulator-min-microvolt = <1050000>;
|
|
regulator-max-microvolt = <1050000>;
|
|
gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
|
|
vin-supply = <&vdd_1v05>;
|
|
};
|
|
|
|
reg_3v3_mxm: regulator-3v3-mxm {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "+V3.3_MXM";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
reg_3v3: regulator-3v3 {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "+V3.3";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
/* PWR_EN_+V3.3 */
|
|
gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
|
|
enable-active-high;
|
|
vin-supply = <®_3v3_mxm>;
|
|
};
|
|
|
|
reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "+V3.3_AVDD_HDMI";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
vin-supply = <&vdd_1v05>;
|
|
};
|
|
|
|
sound {
|
|
compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1",
|
|
"nvidia,tegra-audio-sgtl5000";
|
|
nvidia,model = "Toradex Apalis TK1";
|
|
nvidia,audio-routing =
|
|
"Headphone Jack", "HP_OUT",
|
|
"LINE_IN", "Line In Jack",
|
|
"MIC_IN", "Mic Jack";
|
|
nvidia,i2s-controller = <&tegra_i2s2>;
|
|
nvidia,audio-codec = <&sgtl5000>;
|
|
clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
|
|
<&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
|
|
<&tegra_car TEGRA124_CLK_EXTERN1>;
|
|
clock-names = "pll_a", "pll_a_out0", "mclk";
|
|
};
|
|
|
|
thermal-zones {
|
|
cpu {
|
|
trips {
|
|
cpu-shutdown-trip {
|
|
temperature = <101000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
mem {
|
|
trips {
|
|
mem-shutdown-trip {
|
|
temperature = <101000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpu {
|
|
trips {
|
|
gpu-shutdown-trip {
|
|
temperature = <101000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&gpio {
|
|
/* I210 Gigabit Ethernet Controller Reset */
|
|
lan_reset_n {
|
|
gpio-hog;
|
|
gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
|
|
output-high;
|
|
line-name = "LAN_RESET_N";
|
|
};
|
|
|
|
/* Control MXM3 pin 26 Reset Module Output Carrier Input */
|
|
reset_moci_ctrl {
|
|
gpio-hog;
|
|
gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
|
|
output-high;
|
|
line-name = "RESET_MOCI_CTRL";
|
|
};
|
|
};
|