forked from Minki/linux
207 lines
5.9 KiB
C
207 lines
5.9 KiB
C
/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* vineetg: Jan 1011
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* -sched_clock( ) no longer jiffies based. Uses the same clocksource
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* as gtod
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*
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* Rajeshwarr/Vineetg: Mar 2008
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* -Implemented CONFIG_GENERIC_TIME (rather deleted arch specific code)
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* for arch independent gettimeofday()
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* -Implemented CONFIG_GENERIC_CLOCKEVENTS as base for hrtimers
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*
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* Vineetg: Mar 2008: Forked off from time.c which now is time-jiff.c
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*/
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/* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1
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* Each can programmed to go from @count to @limit and optionally
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* interrupt when that happens.
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* A write to Control Register clears the Interrupt
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*
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* We've designated TIMER0 for events (clockevents)
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* while TIMER1 for free running (clocksource)
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*
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* Newer ARC700 cores have 64bit clk fetching RTSC insn, preferred over TIMER1
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* which however is currently broken
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*/
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/time.h>
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#include <linux/init.h>
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#include <linux/timex.h>
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#include <linux/profile.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <asm/irq.h>
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#include <asm/arcregs.h>
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#include <asm/clk.h>
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#include <asm/mach_desc.h>
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/* Timer related Aux registers */
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#define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
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#define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */
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#define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */
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#define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */
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#define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */
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#define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */
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#define TIMER_CTRL_IE (1 << 0) /* Interupt when Count reachs limit */
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#define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */
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#define ARC_TIMER_MAX 0xFFFFFFFF
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/********** Clock Source Device *********/
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/*
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* set 32bit TIMER1 to keep counting monotonically and wraparound
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*/
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int arc_counter_setup(void)
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{
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write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX);
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write_aux_reg(ARC_REG_TIMER1_CNT, 0);
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write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);
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/* Not usable in SMP */
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return !IS_ENABLED(CONFIG_SMP);
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}
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static cycle_t arc_counter_read(struct clocksource *cs)
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{
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return (cycle_t) read_aux_reg(ARC_REG_TIMER1_CNT);
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}
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static struct clocksource arc_counter = {
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.name = "ARC Timer1",
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.rating = 300,
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.read = arc_counter_read,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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/********** Clock Event Device *********/
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/*
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* Arm the timer to interrupt after @cycles
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* The distinction for oneshot/periodic is done in arc_event_timer_ack() below
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*/
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static void arc_timer_event_setup(unsigned int cycles)
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{
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write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles);
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write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */
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write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH);
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}
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static int arc_clkevent_set_next_event(unsigned long delta,
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struct clock_event_device *dev)
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{
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arc_timer_event_setup(delta);
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return 0;
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}
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static void arc_clkevent_set_mode(enum clock_event_mode mode,
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struct clock_event_device *dev)
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{
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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/*
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* At X Hz, 1 sec = 1000ms -> X cycles;
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* 10ms -> X / 100 cycles
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*/
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arc_timer_event_setup(arc_get_core_freq() / HZ);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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break;
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default:
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break;
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}
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return;
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}
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static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = {
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.name = "ARC Timer0",
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.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
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.mode = CLOCK_EVT_MODE_UNUSED,
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.rating = 300,
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.irq = TIMER0_IRQ, /* hardwired, no need for resources */
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.set_next_event = arc_clkevent_set_next_event,
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.set_mode = arc_clkevent_set_mode,
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};
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static irqreturn_t timer_irq_handler(int irq, void *dev_id)
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{
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/*
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* Note that generic IRQ core could have passed @evt for @dev_id if
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* irq_set_chip_and_handler() asked for handle_percpu_devid_irq()
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*/
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struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
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int irq_reenable = evt->mode == CLOCK_EVT_MODE_PERIODIC;
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/*
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* Any write to CTRL reg ACks the interrupt, we rewrite the
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* Count when [N]ot [H]alted bit.
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* And re-arm it if perioid by [I]nterrupt [E]nable bit
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*/
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write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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/*
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* Setup the local event timer for @cpu
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*/
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void arc_local_timer_setup()
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{
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struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
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int cpu = smp_processor_id();
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evt->cpumask = cpumask_of(cpu);
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clockevents_config_and_register(evt, arc_get_core_freq(),
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0, ARC_TIMER_MAX);
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/* setup the per-cpu timer IRQ handler - for all cpus */
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arc_request_percpu_irq(TIMER0_IRQ, cpu, timer_irq_handler,
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"Timer0 (per-cpu-tick)", evt);
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}
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/*
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* Called from start_kernel() - boot CPU only
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*
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* -Sets up h/w timers as applicable on boot cpu
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* -Also sets up any global state needed for timer subsystem:
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* - for "counting" timer, registers a clocksource, usable across CPUs
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* (provided that underlying counter h/w is synchronized across cores)
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* - for "event" timer, sets up TIMER0 IRQ (as that is platform agnostic)
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*/
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void __init time_init(void)
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{
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/*
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* sets up the timekeeping free-flowing counter which also returns
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* whether the counter is usable as clocksource
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*/
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if (arc_counter_setup())
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/*
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* CLK upto 4.29 GHz can be safely represented in 32 bits
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* because Max 32 bit number is 4,294,967,295
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*/
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clocksource_register_hz(&arc_counter, arc_get_core_freq());
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/* sets up the periodic event timer */
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arc_local_timer_setup();
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if (machine_desc->init_time)
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machine_desc->init_time();
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}
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