forked from Minki/linux
6f83eaa170
This patch extract CSR Register definition into separate header files as most of the definition are commons to both 3945 and 4965. Definitions specific for 3945 and 4965 are properly prefixed Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
571 lines
21 KiB
C
571 lines
21 KiB
C
/******************************************************************************
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
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* USA
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*
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.GPL.
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*
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* Contact Information:
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* James P. Ketrenos <ipw2100-admin@linux.intel.com>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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* BSD LICENSE
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*
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* Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*****************************************************************************/
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/*
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* Please use this file (iwl-3945-hw.h) only for hardware-related definitions.
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* Please use iwl-3945-commands.h for uCode API definitions.
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* Please use iwl-3945.h for driver implementation definitions.
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*/
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#ifndef __iwl_3945_hw__
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#define __iwl_3945_hw__
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/*
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* uCode queue management definitions ...
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* Queue #4 is the command queue for 3945 and 4965.
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*/
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#define IWL_CMD_QUEUE_NUM 4
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/* Tx rates */
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#define IWL_CCK_RATES 4
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#define IWL_OFDM_RATES 8
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#define IWL_HT_RATES 0
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#define IWL_MAX_RATES (IWL_CCK_RATES+IWL_OFDM_RATES+IWL_HT_RATES)
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/* Time constants */
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#define SHORT_SLOT_TIME 9
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#define LONG_SLOT_TIME 20
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/* RSSI to dBm */
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#define IWL_RSSI_OFFSET 95
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/*
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* EEPROM related constants, enums, and structures.
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*/
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/*
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* EEPROM access time values:
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*
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* Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG,
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* then clearing (with subsequent read/modify/write) CSR_EEPROM_REG bit
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* CSR_EEPROM_REG_BIT_CMD (0x2).
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* Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
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* When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
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* Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
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*/
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#define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */
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#define IWL_EEPROM_ACCESS_DELAY 10 /* uSec */
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/*
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* Regulatory channel usage flags in EEPROM struct iwl_eeprom_channel.flags.
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*
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* IBSS and/or AP operation is allowed *only* on those channels with
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* (VALID && IBSS && ACTIVE && !RADAR). This restriction is in place because
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* RADAR detection is not supported by the 3945 driver, but is a
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* requirement for establishing a new network for legal operation on channels
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* requiring RADAR detection or restricting ACTIVE scanning.
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*
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* NOTE: "WIDE" flag indicates that 20 MHz channel is supported;
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* 3945 does not support FAT 40 MHz-wide channels.
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*
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* NOTE: Using a channel inappropriately will result in a uCode error!
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*/
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enum {
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EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */
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EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */
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/* Bit 2 Reserved */
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EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */
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EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */
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EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */
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EEPROM_CHANNEL_NARROW = (1 << 6), /* 10 MHz channel (not used) */
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EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */
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};
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/* SKU Capabilities */
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#define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0)
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#define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1)
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#define EEPROM_SKU_CAP_OP_MODE_MRC (1 << 7)
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/* *regulatory* channel data from eeprom, one for each channel */
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struct iwl3945_eeprom_channel {
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u8 flags; /* flags copied from EEPROM */
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s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */
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} __attribute__ ((packed));
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/*
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* Mapping of a Tx power level, at factory calibration temperature,
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* to a radio/DSP gain table index.
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* One for each of 5 "sample" power levels in each band.
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* v_det is measured at the factory, using the 3945's built-in power amplifier
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* (PA) output voltage detector. This same detector is used during Tx of
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* long packets in normal operation to provide feedback as to proper output
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* level.
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* Data copied from EEPROM.
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* DO NOT ALTER THIS STRUCTURE!!!
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*/
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struct iwl3945_eeprom_txpower_sample {
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u8 gain_index; /* index into power (gain) setup table ... */
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s8 power; /* ... for this pwr level for this chnl group */
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u16 v_det; /* PA output voltage */
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} __attribute__ ((packed));
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/*
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* Mappings of Tx power levels -> nominal radio/DSP gain table indexes.
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* One for each channel group (a.k.a. "band") (1 for BG, 4 for A).
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* Tx power setup code interpolates between the 5 "sample" power levels
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* to determine the nominal setup for a requested power level.
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* Data copied from EEPROM.
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* DO NOT ALTER THIS STRUCTURE!!!
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*/
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struct iwl3945_eeprom_txpower_group {
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struct iwl3945_eeprom_txpower_sample samples[5]; /* 5 power levels */
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s32 a, b, c, d, e; /* coefficients for voltage->power
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* formula (signed) */
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s32 Fa, Fb, Fc, Fd, Fe; /* these modify coeffs based on
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* frequency (signed) */
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s8 saturation_power; /* highest power possible by h/w in this
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* band */
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u8 group_channel; /* "representative" channel # in this band */
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s16 temperature; /* h/w temperature at factory calib this band
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* (signed) */
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} __attribute__ ((packed));
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/*
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* Temperature-based Tx-power compensation data, not band-specific.
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* These coefficients are use to modify a/b/c/d/e coeffs based on
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* difference between current temperature and factory calib temperature.
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* Data copied from EEPROM.
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*/
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struct iwl3945_eeprom_temperature_corr {
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u32 Ta;
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u32 Tb;
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u32 Tc;
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u32 Td;
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u32 Te;
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} __attribute__ ((packed));
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/*
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* EEPROM map
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*/
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struct iwl3945_eeprom {
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u8 reserved0[16];
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#define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */
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u16 device_id; /* abs.ofs: 16 */
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u8 reserved1[2];
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#define EEPROM_PMC (2*0x0A) /* 2 bytes */
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u16 pmc; /* abs.ofs: 20 */
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u8 reserved2[20];
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#define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */
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u8 mac_address[6]; /* abs.ofs: 42 */
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u8 reserved3[58];
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#define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */
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u16 board_revision; /* abs.ofs: 106 */
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u8 reserved4[11];
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#define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */
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u8 board_pba_number[9]; /* abs.ofs: 119 */
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u8 reserved5[8];
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#define EEPROM_VERSION (2*0x44) /* 2 bytes */
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u16 version; /* abs.ofs: 136 */
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#define EEPROM_SKU_CAP (2*0x45) /* 1 bytes */
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u8 sku_cap; /* abs.ofs: 138 */
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#define EEPROM_LEDS_MODE (2*0x45+1) /* 1 bytes */
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u8 leds_mode; /* abs.ofs: 139 */
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#define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */
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u16 oem_mode;
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#define EEPROM_WOWLAN_MODE (2*0x47) /* 2 bytes */
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u16 wowlan_mode; /* abs.ofs: 142 */
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#define EEPROM_LEDS_TIME_INTERVAL (2*0x48) /* 2 bytes */
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u16 leds_time_interval; /* abs.ofs: 144 */
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#define EEPROM_LEDS_OFF_TIME (2*0x49) /* 1 bytes */
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u8 leds_off_time; /* abs.ofs: 146 */
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#define EEPROM_LEDS_ON_TIME (2*0x49+1) /* 1 bytes */
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u8 leds_on_time; /* abs.ofs: 147 */
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#define EEPROM_ALMGOR_M_VERSION (2*0x4A) /* 1 bytes */
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u8 almgor_m_version; /* abs.ofs: 148 */
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#define EEPROM_ANTENNA_SWITCH_TYPE (2*0x4A+1) /* 1 bytes */
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u8 antenna_switch_type; /* abs.ofs: 149 */
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u8 reserved6[42];
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#define EEPROM_REGULATORY_SKU_ID (2*0x60) /* 4 bytes */
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u8 sku_id[4]; /* abs.ofs: 192 */
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/*
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* Per-channel regulatory data.
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*
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* Each channel that *might* be supported by 3945 or 4965 has a fixed location
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* in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory
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* txpower (MSB).
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*
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* Entries immediately below are for 20 MHz channel width. FAT (40 MHz)
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* channels (only for 4965, not supported by 3945) appear later in the EEPROM.
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*
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* 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
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*/
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#define EEPROM_REGULATORY_BAND_1 (2*0x62) /* 2 bytes */
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u16 band_1_count; /* abs.ofs: 196 */
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#define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63) /* 28 bytes */
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struct iwl3945_eeprom_channel band_1_channels[14]; /* abs.ofs: 196 */
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/*
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* 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196,
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* 5.0 GHz channels 7, 8, 11, 12, 16
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* (4915-5080MHz) (none of these is ever supported)
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*/
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#define EEPROM_REGULATORY_BAND_2 (2*0x71) /* 2 bytes */
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u16 band_2_count; /* abs.ofs: 226 */
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#define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72) /* 26 bytes */
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struct iwl3945_eeprom_channel band_2_channels[13]; /* abs.ofs: 228 */
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/*
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* 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
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* (5170-5320MHz)
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*/
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#define EEPROM_REGULATORY_BAND_3 (2*0x7F) /* 2 bytes */
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u16 band_3_count; /* abs.ofs: 254 */
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#define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80) /* 24 bytes */
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struct iwl3945_eeprom_channel band_3_channels[12]; /* abs.ofs: 256 */
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/*
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* 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
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* (5500-5700MHz)
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*/
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#define EEPROM_REGULATORY_BAND_4 (2*0x8C) /* 2 bytes */
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u16 band_4_count; /* abs.ofs: 280 */
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#define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D) /* 22 bytes */
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struct iwl3945_eeprom_channel band_4_channels[11]; /* abs.ofs: 282 */
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/*
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* 5.7 GHz channels 145, 149, 153, 157, 161, 165
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* (5725-5825MHz)
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*/
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#define EEPROM_REGULATORY_BAND_5 (2*0x98) /* 2 bytes */
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u16 band_5_count; /* abs.ofs: 304 */
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#define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99) /* 12 bytes */
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struct iwl3945_eeprom_channel band_5_channels[6]; /* abs.ofs: 306 */
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u8 reserved9[194];
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/*
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* 3945 Txpower calibration data.
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*/
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#define EEPROM_TXPOWER_CALIB_GROUP0 0x200
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#define EEPROM_TXPOWER_CALIB_GROUP1 0x240
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#define EEPROM_TXPOWER_CALIB_GROUP2 0x280
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#define EEPROM_TXPOWER_CALIB_GROUP3 0x2c0
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#define EEPROM_TXPOWER_CALIB_GROUP4 0x300
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#define IWL_NUM_TX_CALIB_GROUPS 5
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struct iwl3945_eeprom_txpower_group groups[IWL_NUM_TX_CALIB_GROUPS];
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/* abs.ofs: 512 */
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#define EEPROM_CALIB_TEMPERATURE_CORRECT 0x340
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struct iwl3945_eeprom_temperature_corr corrections; /* abs.ofs: 832 */
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u8 reserved16[172]; /* fill out to full 1024 byte block */
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} __attribute__ ((packed));
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#define IWL_EEPROM_IMAGE_SIZE 1024
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/* End of EEPROM */
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#include "iwl-3945-commands.h"
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#define PCI_LINK_CTRL 0x0F0
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#define PCI_POWER_SOURCE 0x0C8
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#define PCI_REG_WUM8 0x0E8
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#define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000)
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/*=== HBUS (Host-side Bus) ===*/
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#define HBUS_BASE (0x400)
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/*
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* Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
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* structures, error log, event log, verifying uCode load).
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* First write to address register, then read from or write to data register
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* to complete the job. Once the address register is set up, accesses to
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* data registers auto-increment the address by one dword.
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* Bit usage for address registers (read or write):
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* 0-31: memory address within device
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*/
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#define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c)
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#define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010)
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#define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018)
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#define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c)
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/*
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* Registers for accessing device's internal peripheral registers
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* (e.g. SCD, BSM, etc.). First write to address register,
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* then read from or write to data register to complete the job.
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* Bit usage for address registers (read or write):
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* 0-15: register address (offset) within device
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* 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
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*/
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#define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044)
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#define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048)
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#define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c)
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#define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050)
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/*
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* Per-Tx-queue write pointer (index, really!) (3945 and 4965).
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* Indicates index to next TFD that driver will fill (1 past latest filled).
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* Bit usage:
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* 0-7: queue write index
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* 11-8: queue selector
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*/
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#define HBUS_TARG_WRPTR (HBUS_BASE+0x060)
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/* SCD (3945 Tx Frame Scheduler) */
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#define SCD_BASE (CSR_BASE + 0x2E00)
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#define SCD_MODE_REG (SCD_BASE + 0x000)
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#define SCD_ARASTAT_REG (SCD_BASE + 0x004)
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#define SCD_TXFACT_REG (SCD_BASE + 0x010)
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#define SCD_TXF4MF_REG (SCD_BASE + 0x014)
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#define SCD_TXF5MF_REG (SCD_BASE + 0x020)
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#define SCD_SBYP_MODE_1_REG (SCD_BASE + 0x02C)
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#define SCD_SBYP_MODE_2_REG (SCD_BASE + 0x030)
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/*=== FH (data Flow Handler) ===*/
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#define FH_BASE (0x800)
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#define FH_CBCC_TABLE (FH_BASE+0x140)
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#define FH_TFDB_TABLE (FH_BASE+0x180)
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#define FH_RCSR_TABLE (FH_BASE+0x400)
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#define FH_RSSR_TABLE (FH_BASE+0x4c0)
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#define FH_TCSR_TABLE (FH_BASE+0x500)
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#define FH_TSSR_TABLE (FH_BASE+0x680)
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/* TFDB (Transmit Frame Buffer Descriptor) */
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#define FH_TFDB(_channel, buf) \
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(FH_TFDB_TABLE+((_channel)*2+(buf))*0x28)
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#define ALM_FH_TFDB_CHNL_BUF_CTRL_REG(_channel) \
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(FH_TFDB_TABLE + 0x50 * _channel)
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/* CBCC _channel is [0,2] */
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#define FH_CBCC(_channel) (FH_CBCC_TABLE+(_channel)*0x8)
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#define FH_CBCC_CTRL(_channel) (FH_CBCC(_channel)+0x00)
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#define FH_CBCC_BASE(_channel) (FH_CBCC(_channel)+0x04)
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/* RCSR _channel is [0,2] */
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#define FH_RCSR(_channel) (FH_RCSR_TABLE+(_channel)*0x40)
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#define FH_RCSR_CONFIG(_channel) (FH_RCSR(_channel)+0x00)
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#define FH_RCSR_RBD_BASE(_channel) (FH_RCSR(_channel)+0x04)
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#define FH_RCSR_WPTR(_channel) (FH_RCSR(_channel)+0x20)
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#define FH_RCSR_RPTR_ADDR(_channel) (FH_RCSR(_channel)+0x24)
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#define FH_RSCSR_CHNL0_WPTR (FH_RCSR_WPTR(0))
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/* RSSR */
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#define FH_RSSR_CTRL (FH_RSSR_TABLE+0x000)
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#define FH_RSSR_STATUS (FH_RSSR_TABLE+0x004)
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/* TCSR */
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#define FH_TCSR(_channel) (FH_TCSR_TABLE+(_channel)*0x20)
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#define FH_TCSR_CONFIG(_channel) (FH_TCSR(_channel)+0x00)
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#define FH_TCSR_CREDIT(_channel) (FH_TCSR(_channel)+0x04)
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#define FH_TCSR_BUFF_STTS(_channel) (FH_TCSR(_channel)+0x08)
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/* TSSR */
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#define FH_TSSR_CBB_BASE (FH_TSSR_TABLE+0x000)
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#define FH_TSSR_MSG_CONFIG (FH_TSSR_TABLE+0x008)
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#define FH_TSSR_TX_STATUS (FH_TSSR_TABLE+0x010)
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/* DBM */
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#define ALM_FH_SRVC_CHNL (6)
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#define ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE (20)
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#define ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH (4)
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#define ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN (0x08000000)
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#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE (0x80000000)
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#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE (0x20000000)
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#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 (0x01000000)
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#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST (0x00001000)
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#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH (0x00000000)
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#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
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#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001)
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#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000)
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#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008)
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#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
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#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
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#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
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#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
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#define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00004000)
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#define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001)
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#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000)
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#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000)
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#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400)
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#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100)
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#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080)
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#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020)
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#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005)
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#define ALM_TB_MAX_BYTES_COUNT (0xFFF0)
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#define ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) \
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((1LU << _channel) << 24)
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#define ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel) \
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((1LU << _channel) << 16)
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#define ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_channel) \
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(ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) | \
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ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel))
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#define PCI_CFG_REV_ID_BIT_BASIC_SKU (0x40) /* bit 6 */
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#define PCI_CFG_REV_ID_BIT_RTP (0x80) /* bit 7 */
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#define TFD_QUEUE_MIN 0
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#define TFD_QUEUE_MAX 6
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#define TFD_QUEUE_SIZE_MAX (256)
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#define IWL_NUM_SCAN_RATES (2)
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#define IWL_DEFAULT_TX_RETRY 15
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/*********************************************/
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|
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#define RFD_SIZE 4
|
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#define NUM_TFD_CHUNKS 4
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#define RX_QUEUE_SIZE 256
|
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#define RX_QUEUE_MASK 255
|
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#define RX_QUEUE_SIZE_LOG 8
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#define U32_PAD(n) ((4-(n))&0x3)
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|
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#define TFD_CTL_COUNT_SET(n) (n << 24)
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#define TFD_CTL_COUNT_GET(ctl) ((ctl >> 24) & 7)
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#define TFD_CTL_PAD_SET(n) (n << 28)
|
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#define TFD_CTL_PAD_GET(ctl) (ctl >> 28)
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|
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#define TFD_TX_CMD_SLOTS 256
|
|
#define TFD_CMD_SLOTS 32
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|
|
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#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl3945_cmd) - \
|
|
sizeof(struct iwl3945_cmd_meta))
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|
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/*
|
|
* RX related structures and functions
|
|
*/
|
|
#define RX_FREE_BUFFERS 64
|
|
#define RX_LOW_WATERMARK 8
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|
|
/* Sizes and addresses for instruction and data memory (SRAM) in
|
|
* 3945's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */
|
|
#define RTC_INST_LOWER_BOUND (0x000000)
|
|
#define ALM_RTC_INST_UPPER_BOUND (0x014000)
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|
|
|
#define RTC_DATA_LOWER_BOUND (0x800000)
|
|
#define ALM_RTC_DATA_UPPER_BOUND (0x808000)
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|
|
|
#define ALM_RTC_INST_SIZE (ALM_RTC_INST_UPPER_BOUND - RTC_INST_LOWER_BOUND)
|
|
#define ALM_RTC_DATA_SIZE (ALM_RTC_DATA_UPPER_BOUND - RTC_DATA_LOWER_BOUND)
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|
|
#define IWL_MAX_INST_SIZE ALM_RTC_INST_SIZE
|
|
#define IWL_MAX_DATA_SIZE ALM_RTC_DATA_SIZE
|
|
|
|
/* Size of uCode instruction memory in bootstrap state machine */
|
|
#define IWL_MAX_BSM_SIZE ALM_RTC_INST_SIZE
|
|
|
|
#define IWL_MAX_NUM_QUEUES 8
|
|
|
|
static inline int iwl3945_hw_valid_rtc_data_addr(u32 addr)
|
|
{
|
|
return (addr >= RTC_DATA_LOWER_BOUND) &&
|
|
(addr < ALM_RTC_DATA_UPPER_BOUND);
|
|
}
|
|
|
|
/* Base physical address of iwl3945_shared is provided to FH_TSSR_CBB_BASE
|
|
* and &iwl3945_shared.rx_read_ptr[0] is provided to FH_RCSR_RPTR_ADDR(0) */
|
|
struct iwl3945_shared {
|
|
__le32 tx_base_ptr[8];
|
|
__le32 rx_read_ptr[3];
|
|
} __attribute__ ((packed));
|
|
|
|
struct iwl3945_tfd_frame_data {
|
|
__le32 addr;
|
|
__le32 len;
|
|
} __attribute__ ((packed));
|
|
|
|
struct iwl3945_tfd_frame {
|
|
__le32 control_flags;
|
|
struct iwl3945_tfd_frame_data pa[4];
|
|
u8 reserved[28];
|
|
} __attribute__ ((packed));
|
|
|
|
static inline u8 iwl3945_hw_get_rate(__le16 rate_n_flags)
|
|
{
|
|
return le16_to_cpu(rate_n_flags) & 0xFF;
|
|
}
|
|
|
|
static inline u16 iwl3945_hw_get_rate_n_flags(__le16 rate_n_flags)
|
|
{
|
|
return le16_to_cpu(rate_n_flags);
|
|
}
|
|
|
|
static inline __le16 iwl3945_hw_set_rate_n_flags(u8 rate, u16 flags)
|
|
{
|
|
return cpu_to_le16((u16)rate|flags);
|
|
}
|
|
#endif
|