forked from Minki/linux
4499ce4293
OMAP4 mailbox has a different MAILBOX_SYSCONFIG register. There is now no AutoIdle. The SIDLEMODE bits have been right-shifted by 1 bit and now occupy bits 2 & 3. Signed-off-by: Suman Anna <s-anna@ti.com> Acked-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
491 lines
12 KiB
C
491 lines
12 KiB
C
/*
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* Mailbox reservation modules for OMAP2/3
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*
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* Copyright (C) 2006-2009 Nokia Corporation
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* Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
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* and Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <plat/mailbox.h>
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#include <mach/irqs.h>
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#define DRV_NAME "omap2-mailbox"
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#define MAILBOX_REVISION 0x000
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#define MAILBOX_SYSCONFIG 0x010
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#define MAILBOX_SYSSTATUS 0x014
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#define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
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#define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
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#define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
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#define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
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#define MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
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#define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 10 * (u))
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#define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 10 * (u))
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#define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 10 * (u))
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#define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
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#define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
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/* SYSCONFIG: register bit definition */
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#define AUTOIDLE (1 << 0)
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#define SOFTRESET (1 << 1)
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#define SMARTIDLE (2 << 3)
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#define OMAP4_SOFTRESET (1 << 0)
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#define OMAP4_NOIDLE (1 << 2)
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#define OMAP4_SMARTIDLE (2 << 2)
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/* SYSSTATUS: register bit definition */
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#define RESETDONE (1 << 0)
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#define MBOX_REG_SIZE 0x120
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#define OMAP4_MBOX_REG_SIZE 0x130
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#define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32))
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#define OMAP4_MBOX_NR_REGS (OMAP4_MBOX_REG_SIZE / sizeof(u32))
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static void __iomem *mbox_base;
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struct omap_mbox2_fifo {
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unsigned long msg;
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unsigned long fifo_stat;
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unsigned long msg_stat;
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};
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struct omap_mbox2_priv {
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struct omap_mbox2_fifo tx_fifo;
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struct omap_mbox2_fifo rx_fifo;
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unsigned long irqenable;
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unsigned long irqstatus;
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u32 newmsg_bit;
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u32 notfull_bit;
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u32 ctx[OMAP4_MBOX_NR_REGS];
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unsigned long irqdisable;
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};
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static struct clk *mbox_ick_handle;
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static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
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omap_mbox_type_t irq);
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static inline unsigned int mbox_read_reg(size_t ofs)
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{
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return __raw_readl(mbox_base + ofs);
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}
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static inline void mbox_write_reg(u32 val, size_t ofs)
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{
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__raw_writel(val, mbox_base + ofs);
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}
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/* Mailbox H/W preparations */
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static int omap2_mbox_startup(struct omap_mbox *mbox)
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{
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u32 l;
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unsigned long timeout;
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mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
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if (IS_ERR(mbox_ick_handle)) {
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printk(KERN_ERR "Could not get mailboxes_ick: %ld\n",
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PTR_ERR(mbox_ick_handle));
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return PTR_ERR(mbox_ick_handle);
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}
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clk_enable(mbox_ick_handle);
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if (cpu_is_omap44xx()) {
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mbox_write_reg(OMAP4_SOFTRESET, MAILBOX_SYSCONFIG);
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timeout = jiffies + msecs_to_jiffies(20);
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do {
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l = mbox_read_reg(MAILBOX_SYSCONFIG);
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if (!(l & OMAP4_SOFTRESET))
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break;
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} while (!time_after(jiffies, timeout));
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if (l & OMAP4_SOFTRESET) {
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pr_err("Can't take mailbox out of reset\n");
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return -ENODEV;
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}
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} else {
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mbox_write_reg(SOFTRESET, MAILBOX_SYSCONFIG);
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timeout = jiffies + msecs_to_jiffies(20);
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do {
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l = mbox_read_reg(MAILBOX_SYSSTATUS);
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if (l & RESETDONE)
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break;
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} while (!time_after(jiffies, timeout));
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if (!(l & RESETDONE)) {
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pr_err("Can't take mailbox out of reset\n");
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return -ENODEV;
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}
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}
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l = mbox_read_reg(MAILBOX_REVISION);
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pr_info("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
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if (cpu_is_omap44xx())
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l = OMAP4_SMARTIDLE;
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else
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l = SMARTIDLE | AUTOIDLE;
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mbox_write_reg(l, MAILBOX_SYSCONFIG);
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omap2_mbox_enable_irq(mbox, IRQ_RX);
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return 0;
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}
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static void omap2_mbox_shutdown(struct omap_mbox *mbox)
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{
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clk_disable(mbox_ick_handle);
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clk_put(mbox_ick_handle);
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mbox_ick_handle = NULL;
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}
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/* Mailbox FIFO handle functions */
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static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
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{
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struct omap_mbox2_fifo *fifo =
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&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
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return (mbox_msg_t) mbox_read_reg(fifo->msg);
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}
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static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
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{
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struct omap_mbox2_fifo *fifo =
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&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
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mbox_write_reg(msg, fifo->msg);
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}
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static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
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{
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struct omap_mbox2_fifo *fifo =
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&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
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return (mbox_read_reg(fifo->msg_stat) == 0);
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}
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static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
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{
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struct omap_mbox2_fifo *fifo =
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&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
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return mbox_read_reg(fifo->fifo_stat);
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}
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/* Mailbox IRQ handle functions */
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static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
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omap_mbox_type_t irq)
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{
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struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
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u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
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l = mbox_read_reg(p->irqenable);
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l |= bit;
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mbox_write_reg(l, p->irqenable);
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}
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static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
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omap_mbox_type_t irq)
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{
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struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
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u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
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l = mbox_read_reg(p->irqdisable);
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l &= ~bit;
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mbox_write_reg(l, p->irqdisable);
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}
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static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
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omap_mbox_type_t irq)
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{
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struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
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u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
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mbox_write_reg(bit, p->irqstatus);
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/* Flush posted write for irq status to avoid spurious interrupts */
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mbox_read_reg(p->irqstatus);
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}
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static int omap2_mbox_is_irq(struct omap_mbox *mbox,
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omap_mbox_type_t irq)
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{
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struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
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u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
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u32 enable = mbox_read_reg(p->irqenable);
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u32 status = mbox_read_reg(p->irqstatus);
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return (int)(enable & status & bit);
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}
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static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
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{
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int i;
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struct omap_mbox2_priv *p = mbox->priv;
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int nr_regs;
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if (cpu_is_omap44xx())
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nr_regs = OMAP4_MBOX_NR_REGS;
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else
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nr_regs = MBOX_NR_REGS;
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for (i = 0; i < nr_regs; i++) {
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p->ctx[i] = mbox_read_reg(i * sizeof(u32));
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dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
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i, p->ctx[i]);
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}
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}
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static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
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{
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int i;
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struct omap_mbox2_priv *p = mbox->priv;
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int nr_regs;
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if (cpu_is_omap44xx())
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nr_regs = OMAP4_MBOX_NR_REGS;
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else
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nr_regs = MBOX_NR_REGS;
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for (i = 0; i < nr_regs; i++) {
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mbox_write_reg(p->ctx[i], i * sizeof(u32));
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dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
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i, p->ctx[i]);
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}
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}
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static struct omap_mbox_ops omap2_mbox_ops = {
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.type = OMAP_MBOX_TYPE2,
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.startup = omap2_mbox_startup,
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.shutdown = omap2_mbox_shutdown,
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.fifo_read = omap2_mbox_fifo_read,
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.fifo_write = omap2_mbox_fifo_write,
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.fifo_empty = omap2_mbox_fifo_empty,
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.fifo_full = omap2_mbox_fifo_full,
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.enable_irq = omap2_mbox_enable_irq,
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.disable_irq = omap2_mbox_disable_irq,
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.ack_irq = omap2_mbox_ack_irq,
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.is_irq = omap2_mbox_is_irq,
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.save_ctx = omap2_mbox_save_ctx,
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.restore_ctx = omap2_mbox_restore_ctx,
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};
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/*
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* MAILBOX 0: ARM -> DSP,
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* MAILBOX 1: ARM <- DSP.
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* MAILBOX 2: ARM -> IVA,
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* MAILBOX 3: ARM <- IVA.
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*/
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/* FIXME: the following structs should be filled automatically by the user id */
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/* DSP */
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static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
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.tx_fifo = {
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.msg = MAILBOX_MESSAGE(0),
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.fifo_stat = MAILBOX_FIFOSTATUS(0),
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},
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.rx_fifo = {
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.msg = MAILBOX_MESSAGE(1),
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.msg_stat = MAILBOX_MSGSTATUS(1),
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},
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.irqenable = MAILBOX_IRQENABLE(0),
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.irqstatus = MAILBOX_IRQSTATUS(0),
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.notfull_bit = MAILBOX_IRQ_NOTFULL(0),
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.newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
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.irqdisable = MAILBOX_IRQENABLE(0),
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};
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/* OMAP4 specific data structure. Use the cpu_is_omap4xxx()
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to use this*/
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static struct omap_mbox2_priv omap2_mbox_1_priv = {
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.tx_fifo = {
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.msg = MAILBOX_MESSAGE(0),
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.fifo_stat = MAILBOX_FIFOSTATUS(0),
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},
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.rx_fifo = {
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.msg = MAILBOX_MESSAGE(1),
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.msg_stat = MAILBOX_MSGSTATUS(1),
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},
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.irqenable = OMAP4_MAILBOX_IRQENABLE(0),
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.irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
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.notfull_bit = MAILBOX_IRQ_NOTFULL(0),
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.newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
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.irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
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};
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struct omap_mbox mbox_1_info = {
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.name = "mailbox-1",
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.ops = &omap2_mbox_ops,
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.priv = &omap2_mbox_1_priv,
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};
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EXPORT_SYMBOL(mbox_1_info);
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struct omap_mbox mbox_dsp_info = {
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.name = "dsp",
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.ops = &omap2_mbox_ops,
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.priv = &omap2_mbox_dsp_priv,
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};
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EXPORT_SYMBOL(mbox_dsp_info);
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static struct omap_mbox2_priv omap2_mbox_2_priv = {
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.tx_fifo = {
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.msg = MAILBOX_MESSAGE(3),
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.fifo_stat = MAILBOX_FIFOSTATUS(3),
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},
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.rx_fifo = {
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.msg = MAILBOX_MESSAGE(2),
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.msg_stat = MAILBOX_MSGSTATUS(2),
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},
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.irqenable = OMAP4_MAILBOX_IRQENABLE(0),
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.irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
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.notfull_bit = MAILBOX_IRQ_NOTFULL(3),
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.newmsg_bit = MAILBOX_IRQ_NEWMSG(2),
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.irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
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};
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struct omap_mbox mbox_2_info = {
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.name = "mailbox-2",
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.ops = &omap2_mbox_ops,
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.priv = &omap2_mbox_2_priv,
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};
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EXPORT_SYMBOL(mbox_2_info);
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#if defined(CONFIG_ARCH_OMAP2420) /* IVA */
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static struct omap_mbox2_priv omap2_mbox_iva_priv = {
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.tx_fifo = {
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.msg = MAILBOX_MESSAGE(2),
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.fifo_stat = MAILBOX_FIFOSTATUS(2),
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},
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.rx_fifo = {
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.msg = MAILBOX_MESSAGE(3),
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.msg_stat = MAILBOX_MSGSTATUS(3),
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},
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.irqenable = MAILBOX_IRQENABLE(3),
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.irqstatus = MAILBOX_IRQSTATUS(3),
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.notfull_bit = MAILBOX_IRQ_NOTFULL(2),
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.newmsg_bit = MAILBOX_IRQ_NEWMSG(3),
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.irqdisable = MAILBOX_IRQENABLE(3),
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};
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static struct omap_mbox mbox_iva_info = {
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.name = "iva",
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.ops = &omap2_mbox_ops,
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.priv = &omap2_mbox_iva_priv,
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};
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#endif
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static int __devinit omap2_mbox_probe(struct platform_device *pdev)
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{
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struct resource *res;
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int ret;
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/* MBOX base */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (unlikely(!res)) {
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dev_err(&pdev->dev, "invalid mem resource\n");
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return -ENODEV;
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}
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mbox_base = ioremap(res->start, resource_size(res));
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if (!mbox_base)
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return -ENOMEM;
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/* DSP or IVA2 IRQ */
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res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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if (unlikely(!res)) {
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dev_err(&pdev->dev, "invalid irq resource\n");
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ret = -ENODEV;
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goto err_dsp;
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}
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if (cpu_is_omap44xx()) {
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mbox_1_info.irq = res->start;
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ret = omap_mbox_register(&pdev->dev, &mbox_1_info);
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} else {
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mbox_dsp_info.irq = res->start;
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ret = omap_mbox_register(&pdev->dev, &mbox_dsp_info);
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}
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if (ret)
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goto err_dsp;
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if (cpu_is_omap44xx()) {
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mbox_2_info.irq = res->start;
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ret = omap_mbox_register(&pdev->dev, &mbox_2_info);
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if (ret) {
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omap_mbox_unregister(&mbox_1_info);
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goto err_dsp;
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}
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}
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#if defined(CONFIG_ARCH_OMAP2420) /* IVA */
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if (cpu_is_omap2420()) {
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/* IVA IRQ */
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res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
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if (unlikely(!res)) {
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dev_err(&pdev->dev, "invalid irq resource\n");
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ret = -ENODEV;
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goto err_iva1;
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}
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mbox_iva_info.irq = res->start;
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ret = omap_mbox_register(&pdev->dev, &mbox_iva_info);
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if (ret)
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goto err_iva1;
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}
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#endif
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return 0;
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err_iva1:
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omap_mbox_unregister(&mbox_dsp_info);
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err_dsp:
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iounmap(mbox_base);
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return ret;
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}
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static int __devexit omap2_mbox_remove(struct platform_device *pdev)
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{
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#if defined(CONFIG_ARCH_OMAP2420)
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omap_mbox_unregister(&mbox_iva_info);
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#endif
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if (cpu_is_omap44xx()) {
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omap_mbox_unregister(&mbox_2_info);
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omap_mbox_unregister(&mbox_1_info);
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} else
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omap_mbox_unregister(&mbox_dsp_info);
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iounmap(mbox_base);
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return 0;
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}
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static struct platform_driver omap2_mbox_driver = {
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.probe = omap2_mbox_probe,
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.remove = __devexit_p(omap2_mbox_remove),
|
|
.driver = {
|
|
.name = DRV_NAME,
|
|
},
|
|
};
|
|
|
|
static int __init omap2_mbox_init(void)
|
|
{
|
|
return platform_driver_register(&omap2_mbox_driver);
|
|
}
|
|
|
|
static void __exit omap2_mbox_exit(void)
|
|
{
|
|
platform_driver_unregister(&omap2_mbox_driver);
|
|
}
|
|
|
|
module_init(omap2_mbox_init);
|
|
module_exit(omap2_mbox_exit);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
|
|
MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, Paul Mundt");
|
|
MODULE_ALIAS("platform:"DRV_NAME);
|