forked from Minki/linux
19b06d7fd0
This commit improves the Armada 38x Device Tree to add the CPU reset and PMSU Device Tree nodes as well as the declaration of the enabling method for the CPUs. These are needed to get SMP working on Armada 38x platforms. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397483648-26611-12-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
152 lines
4.3 KiB
Plaintext
152 lines
4.3 KiB
Plaintext
/*
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* Device Tree Include file for Marvell Armada 385 SoC.
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*
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* Copyright (C) 2014 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include "armada-38x.dtsi"
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/ {
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model = "Marvell Armada 385 family SoC";
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compatible = "marvell,armada385", "marvell,armada38x";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "marvell,armada-380-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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};
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};
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soc {
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internal-regs {
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pinctrl {
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compatible = "marvell,mv88f6820-pinctrl";
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reg = <0x18000 0x20>;
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};
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};
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pcie-controller {
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compatible = "marvell,armada-370-pcie";
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status = "disabled";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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msi-parent = <&mpic>;
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bus-range = <0x00 0xff>;
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ranges =
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<0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
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0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
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0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
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0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
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0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
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0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
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0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
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0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
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0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
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0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
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0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
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0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
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/*
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* This port can be either x4 or x1. When
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* configured in x4 by the bootloader, then
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* pcie@4,0 is not available.
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*/
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pcie@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
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0x81000000 0 0 0x81000000 0x1 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 8>;
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status = "disabled";
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};
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/* x1 port */
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pcie@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
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reg = <0x1000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
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0x81000000 0 0 0x81000000 0x2 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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marvell,pcie-port = <1>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 5>;
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status = "disabled";
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};
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/* x1 port */
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pcie@3,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
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reg = <0x1000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
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0x81000000 0 0 0x81000000 0x3 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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marvell,pcie-port = <2>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 6>;
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status = "disabled";
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};
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/*
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* x1 port only available when pcie@1,0 is
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* configured as a x1 port
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*/
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pcie@4,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
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reg = <0x1000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
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0x81000000 0 0 0x81000000 0x4 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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marvell,pcie-port = <3>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 7>;
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status = "disabled";
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};
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};
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};
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};
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