forked from Minki/linux
7aa1aa6ece
ls1 has qe and ls1 has arm cpu. move qe from arch/powerpc to drivers/soc/fsl to adapt to powerpc and arm Signed-off-by: Zhao Qiang <qiang.zhao@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
444 lines
10 KiB
C
444 lines
10 KiB
C
/*
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* Copyright (C) 2006-2010, 2012-2013 Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* Author: Andy Fleming <afleming@freescale.com>
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*
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* Based on 83xx/mpc8360e_pb.c by:
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* Li Yang <LeoLi@freescale.com>
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* Yin Olivia <Hong-hua.Yin@freescale.com>
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*
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* Description:
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* MPC85xx MDS board specific routines.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/reboot.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/major.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/seq_file.h>
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#include <linux/initrd.h>
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#include <linux/fsl_devices.h>
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#include <linux/of_platform.h>
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#include <linux/of_device.h>
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#include <linux/phy.h>
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#include <linux/memblock.h>
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#include <linux/fsl/guts.h>
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#include <linux/atomic.h>
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#include <asm/time.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <asm/irq.h>
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#include <mm/mmu_decl.h>
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#include <asm/prom.h>
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#include <asm/udbg.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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#include <sysdev/simple_gpio.h>
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#include <soc/fsl/qe/qe.h>
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#include <soc/fsl/qe/qe_ic.h>
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#include <asm/mpic.h>
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#include <asm/swiotlb.h>
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#include "smp.h"
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#include "mpc85xx.h"
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(fmt...) udbg_printf(fmt)
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#else
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#define DBG(fmt...)
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#endif
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#define MV88E1111_SCR 0x10
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#define MV88E1111_SCR_125CLK 0x0010
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static int mpc8568_fixup_125_clock(struct phy_device *phydev)
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{
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int scr;
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int err;
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/* Workaround for the 125 CLK Toggle */
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scr = phy_read(phydev, MV88E1111_SCR);
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if (scr < 0)
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return scr;
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err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK));
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if (err)
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return err;
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err = phy_write(phydev, MII_BMCR, BMCR_RESET);
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if (err)
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return err;
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scr = phy_read(phydev, MV88E1111_SCR);
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if (scr < 0)
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return scr;
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err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008);
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return err;
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}
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static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
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{
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int temp;
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int err;
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/* Errata */
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err = phy_write(phydev,29, 0x0006);
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if (err)
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return err;
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temp = phy_read(phydev, 30);
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if (temp < 0)
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return temp;
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temp = (temp & (~0x8000)) | 0x4000;
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err = phy_write(phydev,30, temp);
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if (err)
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return err;
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err = phy_write(phydev,29, 0x000a);
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if (err)
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return err;
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temp = phy_read(phydev, 30);
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if (temp < 0)
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return temp;
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temp = phy_read(phydev, 30);
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if (temp < 0)
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return temp;
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temp &= ~0x0020;
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err = phy_write(phydev,30,temp);
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if (err)
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return err;
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/* Disable automatic MDI/MDIX selection */
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temp = phy_read(phydev, 16);
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if (temp < 0)
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return temp;
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temp &= ~0x0060;
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err = phy_write(phydev,16,temp);
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return err;
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}
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/* ************************************************************************
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*
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* Setup the architecture
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*
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*/
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#ifdef CONFIG_QUICC_ENGINE
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static void __init mpc85xx_mds_reset_ucc_phys(void)
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{
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struct device_node *np;
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static u8 __iomem *bcsr_regs;
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/* Map BCSR area */
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np = of_find_node_by_name(NULL, "bcsr");
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if (!np)
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return;
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bcsr_regs = of_iomap(np, 0);
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of_node_put(np);
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if (!bcsr_regs)
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return;
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if (machine_is(mpc8568_mds)) {
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#define BCSR_UCC1_GETH_EN (0x1 << 7)
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#define BCSR_UCC2_GETH_EN (0x1 << 7)
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#define BCSR_UCC1_MODE_MSK (0x3 << 4)
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#define BCSR_UCC2_MODE_MSK (0x3 << 0)
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/* Turn off UCC1 & UCC2 */
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clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
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clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
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/* Mode is RGMII, all bits clear */
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clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
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BCSR_UCC2_MODE_MSK);
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/* Turn UCC1 & UCC2 on */
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setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
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setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
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} else if (machine_is(mpc8569_mds)) {
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#define BCSR7_UCC12_GETHnRST (0x1 << 2)
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#define BCSR8_UEM_MARVELL_RST (0x1 << 1)
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#define BCSR_UCC_RGMII (0x1 << 6)
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#define BCSR_UCC_RTBI (0x1 << 5)
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/*
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* U-Boot mangles interrupt polarity for Marvell PHYs,
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* so reset built-in and UEM Marvell PHYs, this puts
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* the PHYs into their normal state.
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*/
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clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
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setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
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setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
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clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
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for_each_compatible_node(np, "network", "ucc_geth") {
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const unsigned int *prop;
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int ucc_num;
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prop = of_get_property(np, "cell-index", NULL);
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if (prop == NULL)
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continue;
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ucc_num = *prop - 1;
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prop = of_get_property(np, "phy-connection-type", NULL);
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if (prop == NULL)
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continue;
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if (strcmp("rtbi", (const char *)prop) == 0)
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clrsetbits_8(&bcsr_regs[7 + ucc_num],
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BCSR_UCC_RGMII, BCSR_UCC_RTBI);
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}
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} else if (machine_is(p1021_mds)) {
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#define BCSR11_ENET_MICRST (0x1 << 5)
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/* Reset Micrel PHY */
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clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
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setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
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}
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iounmap(bcsr_regs);
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}
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static void __init mpc85xx_mds_qe_init(void)
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{
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struct device_node *np;
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mpc85xx_qe_init();
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mpc85xx_qe_par_io_init();
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mpc85xx_mds_reset_ucc_phys();
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if (machine_is(p1021_mds)) {
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struct ccsr_guts __iomem *guts;
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np = of_find_node_by_name(NULL, "global-utilities");
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if (np) {
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guts = of_iomap(np, 0);
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if (!guts)
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pr_err("mpc85xx-rdb: could not map global utilities register\n");
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else{
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/* P1021 has pins muxed for QE and other functions. To
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* enable QE UEC mode, we need to set bit QE0 for UCC1
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* in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
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* and QE12 for QE MII management signals in PMUXCR
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* register.
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*/
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setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
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MPC85xx_PMUXCR_QE(3) |
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MPC85xx_PMUXCR_QE(9) |
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MPC85xx_PMUXCR_QE(12));
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iounmap(guts);
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}
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of_node_put(np);
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}
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}
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}
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static void __init mpc85xx_mds_qeic_init(void)
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{
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struct device_node *np;
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np = of_find_compatible_node(NULL, NULL, "fsl,qe");
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if (!of_device_is_available(np)) {
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of_node_put(np);
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return;
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}
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np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
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if (!np) {
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np = of_find_node_by_type(NULL, "qeic");
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if (!np)
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return;
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}
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if (machine_is(p1021_mds))
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qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
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qe_ic_cascade_high_mpic);
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else
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qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
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of_node_put(np);
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}
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#else
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static void __init mpc85xx_mds_qe_init(void) { }
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static void __init mpc85xx_mds_qeic_init(void) { }
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#endif /* CONFIG_QUICC_ENGINE */
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static void __init mpc85xx_mds_setup_arch(void)
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{
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if (ppc_md.progress)
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ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
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mpc85xx_smp_init();
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mpc85xx_mds_qe_init();
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fsl_pci_assign_primary();
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swiotlb_detect_4g();
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}
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static int __init board_fixups(void)
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{
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char phy_id[20];
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char *compstrs[2] = {"fsl,gianfar-mdio", "fsl,ucc-mdio"};
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struct device_node *mdio;
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struct resource res;
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int i;
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for (i = 0; i < ARRAY_SIZE(compstrs); i++) {
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mdio = of_find_compatible_node(NULL, NULL, compstrs[i]);
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of_address_to_resource(mdio, 0, &res);
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snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
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(unsigned long long)res.start, 1);
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phy_register_fixup_for_id(phy_id, mpc8568_fixup_125_clock);
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phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
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/* Register a workaround for errata */
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snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
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(unsigned long long)res.start, 7);
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phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
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of_node_put(mdio);
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}
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return 0;
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}
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machine_arch_initcall(mpc8568_mds, board_fixups);
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machine_arch_initcall(mpc8569_mds, board_fixups);
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static int __init mpc85xx_publish_devices(void)
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{
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if (machine_is(mpc8568_mds))
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simple_gpiochip_init("fsl,mpc8568mds-bcsr-gpio");
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if (machine_is(mpc8569_mds))
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simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
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return mpc85xx_common_publish_devices();
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}
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machine_arch_initcall(mpc8568_mds, mpc85xx_publish_devices);
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machine_arch_initcall(mpc8569_mds, mpc85xx_publish_devices);
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machine_arch_initcall(p1021_mds, mpc85xx_common_publish_devices);
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machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier);
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machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier);
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machine_arch_initcall(p1021_mds, swiotlb_setup_bus_notifier);
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static void __init mpc85xx_mds_pic_init(void)
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{
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struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
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MPIC_SINGLE_DEST_CPU,
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0, 256, " OpenPIC ");
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BUG_ON(mpic == NULL);
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mpic_init(mpic);
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mpc85xx_mds_qeic_init();
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}
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static int __init mpc85xx_mds_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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return of_flat_dt_is_compatible(root, "MPC85xxMDS");
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}
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define_machine(mpc8568_mds) {
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.name = "MPC8568 MDS",
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.probe = mpc85xx_mds_probe,
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.setup_arch = mpc85xx_mds_setup_arch,
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.init_IRQ = mpc85xx_mds_pic_init,
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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#ifdef CONFIG_PCI
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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#endif
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};
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static int __init mpc8569_mds_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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return of_flat_dt_is_compatible(root, "fsl,MPC8569EMDS");
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}
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define_machine(mpc8569_mds) {
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.name = "MPC8569 MDS",
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.probe = mpc8569_mds_probe,
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.setup_arch = mpc85xx_mds_setup_arch,
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.init_IRQ = mpc85xx_mds_pic_init,
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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#ifdef CONFIG_PCI
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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#endif
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};
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static int __init p1021_mds_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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return of_flat_dt_is_compatible(root, "fsl,P1021MDS");
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}
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define_machine(p1021_mds) {
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.name = "P1021 MDS",
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.probe = p1021_mds_probe,
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.setup_arch = mpc85xx_mds_setup_arch,
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.init_IRQ = mpc85xx_mds_pic_init,
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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#ifdef CONFIG_PCI
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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#endif
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};
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