Jan Kotas 6ded416d4a media: Fix Lane mapping in Cadence CSI2TX ... This patch fixes mapping of lanes in DPHY_CFG register of the controller. In the register, bit 0 means first data lane. In Linux we currently assume lane 0 is clock. Signed-off-by: Jan Kotas <jank@cadence.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>		2019-07-25 06:43:01 -04:00
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cdns-csi2rx.c	media: v4l: fwnode: Initialise the V4L2 fwnode endpoints to zero	2018-10-04 16:21:02 -04:00
cdns-csi2tx.c	media: Fix Lane mapping in Cadence CSI2TX	2019-07-25 06:43:01 -04:00
Kconfig	treewide: Add SPDX license identifier - Makefile/Kconfig	2019-05-21 10:50:46 +02:00
Makefile	media: v4l: cadence: Add Cadence MIPI-CSI2 TX driver	2018-05-17 06:22:08 -04:00