be8454afc5
-----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJdLMSbAAoJEAx081l5xIa+udkP/iWr8mw44tWYb8Wuzc/aR91v 02X/J4S9XTQttNn/1Gpq9ItTLMf0Gc08tk1wEBBHAWi/qGaGZS2al+rv0afeuuQa aFhQzioDi7K/YZt92iEJhdx7wVMyydICTg3INmYlSP7/FyzLp6gBQRGSJ1kX5mHZ qWsFZgUOH9V5evyB6fDMleDaqFOKfcwrD7XYwbOheL/HeYQSv5AYn3VBupBFQ76L 0hclI5VzZQ5V0nnqRTNDQVA9Yl6NTl+2eXTn5vuBtwKXEI6JJw8eihZp2oZDXqfS L441w7wGbkRPzN5kjMZjs1ToPMTlMveR5kL6Sc+o3DT/HmIr1odeaSDXR/93UOLd z0CRJ6xMC8h1ThLNHp8UgbxCKqIwYPsY2wVqjsJt7lDY5jma7Yv2YJ9ocYGHN/sO DVHcU6ugbwvuC5wZZtVZl5J4hjnBZwNRGSVK+iM0tkjalgdEuSFehXT7eQ8SphF/ yI5gD1xNEwGfZ4bvZ3u/QrDCcpUAgPIUYmxEa2tPJILQWOJ9O87yc0y9Z21k9Ef1 9yDqrFV3sPqC2xj/0ufZG/18+Yt99Ykg1jQE3RGDwD/59KAeqPbOvqTKyVODV9jE qje6ScSIc2G0713uss2bcaD3k+rCB5YL2JkKrk5OWW/T2+n9T+JFaiNh7dnSFFcU gBKyeY24OyCDMwXrby0K =SI+Y -----END PGP SIGNATURE----- Merge tag 'drm-next-2019-07-16' of git://anongit.freedesktop.org/drm/drm Pull drm updates from Dave Airlie: "The biggest thing in this is the AMD Navi GPU support, this again contains a bunch of header files that are large. These are the new AMD RX5700 GPUs that just recently became available. New drivers: - ST-Ericsson MCDE driver - Ingenic JZ47xx SoC UAPI change: - HDR source metadata property Core: - HDR inforframes and EDID parsing - drm hdmi infoframe unpacking - remove prime sg_table caching into dma-buf - New gem vram helpers to reduce driver code - Lots of drmP.h removal - reservation fencing fix - documentation updates - drm_fb_helper_connector removed - mode name command handler rewrite fbcon: - Remove the fbcon notifiers ttm: - forward progress fixes dma-buf: - make mmap call optional - debugfs refcount fixes - dma-fence free with pending signals fix - each dma-buf gets an inode Panels: - Lots of additional panel bindings amdgpu: - initial navi10 support - avoid hw reset - HDR metadata support - new thermal sensors for vega asics - RAS fixes - use HMM rather than MMU notifier - xgmi topology via kfd - SR-IOV fixes - driver reload fixes - DC use a core bpc attribute - Aux fixes for DC - Bandwidth calc updates for DC - Clock handling refactor - kfd VEGAM support vmwgfx: - Coherent memory support changes i915: - HDR Support - HDMI i2c link - Icelake multi-segmented gamma support - GuC firmware update - Mule Creek Canyon PCH support for EHL - EHL platform updtes - move i915.alpha_support to i915.force_probe - runtime PM refactoring - VBT parsing refactoring - DSI fixes - struct mutex dependency reduction - GEM code reorg mali-dp: - Komeda driver features msm: - dsi vs EPROBE_DEFER fixes - msm8998 snapdragon 835 support - a540 gpu support - mdp5 and dpu interconnect support exynos: - drmP.h removal tegra: - misc fixes tda998x: - audio support improvements - pixel repeated mode support - quantisation range handling corrections - HDMI vendor info fix armada: - interlace support fix - overlay/video plane register handling refactor - add gamma support rockchip: - RX3328 support panfrost: - expose perf counters via hidden ioctls vkms: - enumerate CRC sources list ast: - rework BO handling mgag200: - rework BO handling dw-hdmi: - suspend/resume support rcar-du: - R8A774A1 Soc Support - LVDS dual-link mode support - Additional formats - Misc fixes omapdrm: - DSI command mode display support stm - fb modifier support - runtime PM support sun4i: - use vmap ops vc4: - binner bo binding rework v3d: - compute shader support - resync/sync fixes - job management refactoring lima: - NULL pointer in irq handler fix - scheduler default timeout virtio: - fence seqno support - trace events bochs: - misc fixes tc458767: - IRQ/HDP handling sii902x: - HDMI audio support atmel-hlcdc: - misc fixes meson: - zpos support" * tag 'drm-next-2019-07-16' of git://anongit.freedesktop.org/drm/drm: (1815 commits) Revert "Merge branch 'vmwgfx-next' of git://people.freedesktop.org/~thomash/linux into drm-next" Revert "mm: adjust apply_to_pfn_range interface for dropped token." mm: adjust apply_to_pfn_range interface for dropped token. drm/amdgpu/navi10: add uclk activity sensor drm/amdgpu: properly guard the generic discovery code drm/amdgpu: add missing documentation on new module parameters drm/amdgpu: don't invalidate caches in RELEASE_MEM, only do the writeback drm/amd/display: avoid 64-bit division drm/amdgpu/psp11: simplify the ucode register logic drm/amdgpu: properly guard DC support in navi code drm/amd/powerplay: vega20: fix uninitialized variable use drm/amd/display: dcn20: include linux/delay.h amdgpu: make pmu support optional drm/amd/powerplay: Zero initialize current_rpm in vega20_get_fan_speed_percent drm/amd/powerplay: Zero initialize freq in smu_v11_0_get_current_clk_freq drm/amd/powerplay: Use memset to initialize metrics structs drm/amdgpu/mes10.1: Fix header guard drm/amd/powerplay: add temperature sensor support for navi10 drm/amdgpu: fix scheduler timeout calc drm/amdgpu: Prepare for hmm_range_register API change (v2) ...
394 lines
11 KiB
C
394 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*/
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#include <drm/drm_damage_helper.h>
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#include "mdp4_kms.h"
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#define DOWN_SCALE_MAX 8
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#define UP_SCALE_MAX 8
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struct mdp4_plane {
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struct drm_plane base;
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const char *name;
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enum mdp4_pipe pipe;
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uint32_t caps;
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uint32_t nformats;
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uint32_t formats[32];
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bool enabled;
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};
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#define to_mdp4_plane(x) container_of(x, struct mdp4_plane, base)
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/* MDP format helper functions */
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static inline
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enum mdp4_frame_format mdp4_get_frame_format(struct drm_framebuffer *fb)
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{
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bool is_tile = false;
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if (fb->modifier == DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
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is_tile = true;
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if (fb->format->format == DRM_FORMAT_NV12 && is_tile)
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return FRAME_TILE_YCBCR_420;
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return FRAME_LINEAR;
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}
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static void mdp4_plane_set_scanout(struct drm_plane *plane,
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struct drm_framebuffer *fb);
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static int mdp4_plane_mode_set(struct drm_plane *plane,
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struct drm_crtc *crtc, struct drm_framebuffer *fb,
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int crtc_x, int crtc_y,
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unsigned int crtc_w, unsigned int crtc_h,
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uint32_t src_x, uint32_t src_y,
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uint32_t src_w, uint32_t src_h);
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static struct mdp4_kms *get_kms(struct drm_plane *plane)
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{
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struct msm_drm_private *priv = plane->dev->dev_private;
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return to_mdp4_kms(to_mdp_kms(priv->kms));
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}
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static void mdp4_plane_destroy(struct drm_plane *plane)
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{
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struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
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drm_plane_cleanup(plane);
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kfree(mdp4_plane);
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}
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/* helper to install properties which are common to planes and crtcs */
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static void mdp4_plane_install_properties(struct drm_plane *plane,
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struct drm_mode_object *obj)
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{
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// XXX
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}
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static int mdp4_plane_set_property(struct drm_plane *plane,
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struct drm_property *property, uint64_t val)
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{
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// XXX
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return -EINVAL;
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}
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static const struct drm_plane_funcs mdp4_plane_funcs = {
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.update_plane = drm_atomic_helper_update_plane,
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.disable_plane = drm_atomic_helper_disable_plane,
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.destroy = mdp4_plane_destroy,
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.set_property = mdp4_plane_set_property,
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.reset = drm_atomic_helper_plane_reset,
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.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
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.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
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};
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static void mdp4_plane_cleanup_fb(struct drm_plane *plane,
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struct drm_plane_state *old_state)
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{
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struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
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struct mdp4_kms *mdp4_kms = get_kms(plane);
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struct msm_kms *kms = &mdp4_kms->base.base;
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struct drm_framebuffer *fb = old_state->fb;
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if (!fb)
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return;
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DBG("%s: cleanup: FB[%u]", mdp4_plane->name, fb->base.id);
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msm_framebuffer_cleanup(fb, kms->aspace);
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}
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static int mdp4_plane_atomic_check(struct drm_plane *plane,
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struct drm_plane_state *state)
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{
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return 0;
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}
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static void mdp4_plane_atomic_update(struct drm_plane *plane,
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struct drm_plane_state *old_state)
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{
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struct drm_plane_state *state = plane->state;
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int ret;
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ret = mdp4_plane_mode_set(plane,
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state->crtc, state->fb,
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state->crtc_x, state->crtc_y,
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state->crtc_w, state->crtc_h,
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state->src_x, state->src_y,
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state->src_w, state->src_h);
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/* atomic_check should have ensured that this doesn't fail */
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WARN_ON(ret < 0);
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}
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static const struct drm_plane_helper_funcs mdp4_plane_helper_funcs = {
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.prepare_fb = msm_atomic_prepare_fb,
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.cleanup_fb = mdp4_plane_cleanup_fb,
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.atomic_check = mdp4_plane_atomic_check,
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.atomic_update = mdp4_plane_atomic_update,
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};
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static void mdp4_plane_set_scanout(struct drm_plane *plane,
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struct drm_framebuffer *fb)
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{
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struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
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struct mdp4_kms *mdp4_kms = get_kms(plane);
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struct msm_kms *kms = &mdp4_kms->base.base;
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enum mdp4_pipe pipe = mdp4_plane->pipe;
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mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_STRIDE_A(pipe),
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MDP4_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) |
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MDP4_PIPE_SRC_STRIDE_A_P1(fb->pitches[1]));
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mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_STRIDE_B(pipe),
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MDP4_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) |
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MDP4_PIPE_SRC_STRIDE_B_P3(fb->pitches[3]));
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mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP0_BASE(pipe),
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msm_framebuffer_iova(fb, kms->aspace, 0));
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mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP1_BASE(pipe),
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msm_framebuffer_iova(fb, kms->aspace, 1));
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mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP2_BASE(pipe),
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msm_framebuffer_iova(fb, kms->aspace, 2));
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mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP3_BASE(pipe),
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msm_framebuffer_iova(fb, kms->aspace, 3));
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}
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static void mdp4_write_csc_config(struct mdp4_kms *mdp4_kms,
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enum mdp4_pipe pipe, struct csc_cfg *csc)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(csc->matrix); i++) {
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mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_MV(pipe, i),
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csc->matrix[i]);
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}
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for (i = 0; i < ARRAY_SIZE(csc->post_bias) ; i++) {
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mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_PRE_BV(pipe, i),
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csc->pre_bias[i]);
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mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_POST_BV(pipe, i),
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csc->post_bias[i]);
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}
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for (i = 0; i < ARRAY_SIZE(csc->post_clamp) ; i++) {
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mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_PRE_LV(pipe, i),
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csc->pre_clamp[i]);
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mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_POST_LV(pipe, i),
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csc->post_clamp[i]);
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}
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}
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#define MDP4_VG_PHASE_STEP_DEFAULT 0x20000000
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static int mdp4_plane_mode_set(struct drm_plane *plane,
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struct drm_crtc *crtc, struct drm_framebuffer *fb,
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int crtc_x, int crtc_y,
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unsigned int crtc_w, unsigned int crtc_h,
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uint32_t src_x, uint32_t src_y,
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uint32_t src_w, uint32_t src_h)
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{
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struct drm_device *dev = plane->dev;
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struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
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struct mdp4_kms *mdp4_kms = get_kms(plane);
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enum mdp4_pipe pipe = mdp4_plane->pipe;
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const struct mdp_format *format;
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uint32_t op_mode = 0;
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uint32_t phasex_step = MDP4_VG_PHASE_STEP_DEFAULT;
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uint32_t phasey_step = MDP4_VG_PHASE_STEP_DEFAULT;
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enum mdp4_frame_format frame_type;
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if (!(crtc && fb)) {
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DBG("%s: disabled!", mdp4_plane->name);
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return 0;
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}
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frame_type = mdp4_get_frame_format(fb);
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/* src values are in Q16 fixed point, convert to integer: */
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src_x = src_x >> 16;
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src_y = src_y >> 16;
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src_w = src_w >> 16;
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src_h = src_h >> 16;
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DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", mdp4_plane->name,
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fb->base.id, src_x, src_y, src_w, src_h,
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crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
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format = to_mdp_format(msm_framebuffer_format(fb));
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if (src_w > (crtc_w * DOWN_SCALE_MAX)) {
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DRM_DEV_ERROR(dev->dev, "Width down scaling exceeds limits!\n");
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return -ERANGE;
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}
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if (src_h > (crtc_h * DOWN_SCALE_MAX)) {
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DRM_DEV_ERROR(dev->dev, "Height down scaling exceeds limits!\n");
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return -ERANGE;
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}
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if (crtc_w > (src_w * UP_SCALE_MAX)) {
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DRM_DEV_ERROR(dev->dev, "Width up scaling exceeds limits!\n");
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return -ERANGE;
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}
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if (crtc_h > (src_h * UP_SCALE_MAX)) {
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DRM_DEV_ERROR(dev->dev, "Height up scaling exceeds limits!\n");
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return -ERANGE;
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}
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if (src_w != crtc_w) {
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uint32_t sel_unit = SCALE_FIR;
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op_mode |= MDP4_PIPE_OP_MODE_SCALEX_EN;
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if (MDP_FORMAT_IS_YUV(format)) {
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if (crtc_w > src_w)
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sel_unit = SCALE_PIXEL_RPT;
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else if (crtc_w <= (src_w / 4))
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sel_unit = SCALE_MN_PHASE;
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op_mode |= MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(sel_unit);
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phasex_step = mult_frac(MDP4_VG_PHASE_STEP_DEFAULT,
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src_w, crtc_w);
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}
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}
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if (src_h != crtc_h) {
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uint32_t sel_unit = SCALE_FIR;
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op_mode |= MDP4_PIPE_OP_MODE_SCALEY_EN;
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if (MDP_FORMAT_IS_YUV(format)) {
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if (crtc_h > src_h)
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sel_unit = SCALE_PIXEL_RPT;
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else if (crtc_h <= (src_h / 4))
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sel_unit = SCALE_MN_PHASE;
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op_mode |= MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(sel_unit);
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phasey_step = mult_frac(MDP4_VG_PHASE_STEP_DEFAULT,
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src_h, crtc_h);
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}
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}
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mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_SIZE(pipe),
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MDP4_PIPE_SRC_SIZE_WIDTH(src_w) |
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MDP4_PIPE_SRC_SIZE_HEIGHT(src_h));
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mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_XY(pipe),
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MDP4_PIPE_SRC_XY_X(src_x) |
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MDP4_PIPE_SRC_XY_Y(src_y));
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mdp4_write(mdp4_kms, REG_MDP4_PIPE_DST_SIZE(pipe),
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MDP4_PIPE_DST_SIZE_WIDTH(crtc_w) |
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MDP4_PIPE_DST_SIZE_HEIGHT(crtc_h));
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mdp4_write(mdp4_kms, REG_MDP4_PIPE_DST_XY(pipe),
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MDP4_PIPE_DST_XY_X(crtc_x) |
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MDP4_PIPE_DST_XY_Y(crtc_y));
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mdp4_plane_set_scanout(plane, fb);
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mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_FORMAT(pipe),
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MDP4_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
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MDP4_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
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MDP4_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
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MDP4_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
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COND(format->alpha_enable, MDP4_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
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MDP4_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
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MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
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MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(format->fetch_type) |
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MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample) |
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MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(frame_type) |
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COND(format->unpack_tight, MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT));
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mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_UNPACK(pipe),
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MDP4_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
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MDP4_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
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MDP4_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
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MDP4_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
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if (MDP_FORMAT_IS_YUV(format)) {
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struct csc_cfg *csc = mdp_get_default_csc_cfg(CSC_YUV2RGB);
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op_mode |= MDP4_PIPE_OP_MODE_SRC_YCBCR;
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op_mode |= MDP4_PIPE_OP_MODE_CSC_EN;
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mdp4_write_csc_config(mdp4_kms, pipe, csc);
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}
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mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(pipe), op_mode);
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mdp4_write(mdp4_kms, REG_MDP4_PIPE_PHASEX_STEP(pipe), phasex_step);
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mdp4_write(mdp4_kms, REG_MDP4_PIPE_PHASEY_STEP(pipe), phasey_step);
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if (frame_type != FRAME_LINEAR)
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mdp4_write(mdp4_kms, REG_MDP4_PIPE_SSTILE_FRAME_SIZE(pipe),
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MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(src_w) |
|
|
MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(src_h));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const char *pipe_names[] = {
|
|
"VG1", "VG2",
|
|
"RGB1", "RGB2", "RGB3",
|
|
"VG3", "VG4",
|
|
};
|
|
|
|
enum mdp4_pipe mdp4_plane_pipe(struct drm_plane *plane)
|
|
{
|
|
struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
|
|
return mdp4_plane->pipe;
|
|
}
|
|
|
|
/* initialize plane */
|
|
struct drm_plane *mdp4_plane_init(struct drm_device *dev,
|
|
enum mdp4_pipe pipe_id, bool private_plane)
|
|
{
|
|
struct drm_plane *plane = NULL;
|
|
struct mdp4_plane *mdp4_plane;
|
|
int ret;
|
|
enum drm_plane_type type;
|
|
|
|
mdp4_plane = kzalloc(sizeof(*mdp4_plane), GFP_KERNEL);
|
|
if (!mdp4_plane) {
|
|
ret = -ENOMEM;
|
|
goto fail;
|
|
}
|
|
|
|
plane = &mdp4_plane->base;
|
|
|
|
mdp4_plane->pipe = pipe_id;
|
|
mdp4_plane->name = pipe_names[pipe_id];
|
|
mdp4_plane->caps = mdp4_pipe_caps(pipe_id);
|
|
|
|
mdp4_plane->nformats = mdp_get_formats(mdp4_plane->formats,
|
|
ARRAY_SIZE(mdp4_plane->formats),
|
|
!pipe_supports_yuv(mdp4_plane->caps));
|
|
|
|
type = private_plane ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY;
|
|
ret = drm_universal_plane_init(dev, plane, 0xff, &mdp4_plane_funcs,
|
|
mdp4_plane->formats, mdp4_plane->nformats,
|
|
NULL, type, NULL);
|
|
if (ret)
|
|
goto fail;
|
|
|
|
drm_plane_helper_add(plane, &mdp4_plane_helper_funcs);
|
|
|
|
mdp4_plane_install_properties(plane, &plane->base);
|
|
|
|
drm_plane_enable_fb_damage_clips(plane);
|
|
|
|
return plane;
|
|
|
|
fail:
|
|
if (plane)
|
|
mdp4_plane_destroy(plane);
|
|
|
|
return ERR_PTR(ret);
|
|
}
|