forked from Minki/linux
a78c942df6
While not a port to KVM (yet), this change modifies the kernel to be able to build either at PL1 or at PL2 with a suitable config switch. Pushing up this change avoids handling branch merge issues going forward with the KVM work. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
1086 lines
31 KiB
C
1086 lines
31 KiB
C
/*
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* Copyright (C) 1995 Linus Torvalds
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#include <linux/module.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/ptrace.h>
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#include <linux/mman.h>
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#include <linux/mm.h>
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#include <linux/hugetlb.h>
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#include <linux/swap.h>
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#include <linux/smp.h>
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#include <linux/init.h>
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#include <linux/highmem.h>
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#include <linux/pagemap.h>
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#include <linux/poison.h>
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#include <linux/bootmem.h>
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#include <linux/slab.h>
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#include <linux/proc_fs.h>
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#include <linux/efi.h>
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#include <linux/memory_hotplug.h>
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#include <linux/uaccess.h>
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#include <asm/mmu_context.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/pgtable.h>
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#include <asm/pgalloc.h>
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#include <asm/dma.h>
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#include <asm/fixmap.h>
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#include <asm/tlb.h>
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#include <asm/tlbflush.h>
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#include <asm/sections.h>
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#include <asm/setup.h>
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#include <asm/homecache.h>
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#include <hv/hypervisor.h>
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#include <arch/chip.h>
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#include "migrate.h"
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/*
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* We could set FORCE_MAX_ZONEORDER to "(HPAGE_SHIFT - PAGE_SHIFT + 1)"
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* in the Tile Kconfig, but this generates configure warnings.
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* Do it here and force people to get it right to compile this file.
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* The problem is that with 4KB small pages and 16MB huge pages,
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* the default value doesn't allow us to group enough small pages
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* together to make up a huge page.
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*/
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#if CONFIG_FORCE_MAX_ZONEORDER < HPAGE_SHIFT - PAGE_SHIFT + 1
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# error "Change FORCE_MAX_ZONEORDER in arch/tile/Kconfig to match page size"
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#endif
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#define clear_pgd(pmdptr) (*(pmdptr) = hv_pte(0))
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#ifndef __tilegx__
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unsigned long VMALLOC_RESERVE = CONFIG_VMALLOC_RESERVE;
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#endif
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DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
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/* Create an L2 page table */
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static pte_t * __init alloc_pte(void)
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{
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return __alloc_bootmem(L2_KERNEL_PGTABLE_SIZE, HV_PAGE_TABLE_ALIGN, 0);
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}
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/*
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* L2 page tables per controller. We allocate these all at once from
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* the bootmem allocator and store them here. This saves on kernel L2
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* page table memory, compared to allocating a full 64K page per L2
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* page table, and also means that in cases where we use huge pages,
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* we are guaranteed to later be able to shatter those huge pages and
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* switch to using these page tables instead, without requiring
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* further allocation. Each l2_ptes[] entry points to the first page
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* table for the first hugepage-size piece of memory on the
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* controller; other page tables are just indexed directly, i.e. the
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* L2 page tables are contiguous in memory for each controller.
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*/
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static pte_t *l2_ptes[MAX_NUMNODES];
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static int num_l2_ptes[MAX_NUMNODES];
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static void init_prealloc_ptes(int node, int pages)
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{
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BUG_ON(pages & (HV_L2_ENTRIES-1));
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if (pages) {
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num_l2_ptes[node] = pages;
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l2_ptes[node] = __alloc_bootmem(pages * sizeof(pte_t),
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HV_PAGE_TABLE_ALIGN, 0);
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}
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}
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pte_t *get_prealloc_pte(unsigned long pfn)
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{
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int node = pfn_to_nid(pfn);
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pfn &= ~(-1UL << (NR_PA_HIGHBIT_SHIFT - PAGE_SHIFT));
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BUG_ON(node >= MAX_NUMNODES);
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BUG_ON(pfn >= num_l2_ptes[node]);
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return &l2_ptes[node][pfn];
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}
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/*
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* What caching do we expect pages from the heap to have when
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* they are allocated during bootup? (Once we've installed the
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* "real" swapper_pg_dir.)
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*/
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static int initial_heap_home(void)
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{
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#if CHIP_HAS_CBOX_HOME_MAP()
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if (hash_default)
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return PAGE_HOME_HASH;
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#endif
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return smp_processor_id();
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}
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/*
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* Place a pointer to an L2 page table in a middle page
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* directory entry.
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*/
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static void __init assign_pte(pmd_t *pmd, pte_t *page_table)
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{
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phys_addr_t pa = __pa(page_table);
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unsigned long l2_ptfn = pa >> HV_LOG2_PAGE_TABLE_ALIGN;
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pte_t pteval = hv_pte_set_ptfn(__pgprot(_PAGE_TABLE), l2_ptfn);
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BUG_ON((pa & (HV_PAGE_TABLE_ALIGN-1)) != 0);
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pteval = pte_set_home(pteval, initial_heap_home());
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*(pte_t *)pmd = pteval;
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if (page_table != (pte_t *)pmd_page_vaddr(*pmd))
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BUG();
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}
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#ifdef __tilegx__
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#if HV_L1_SIZE != HV_L2_SIZE
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# error Rework assumption that L1 and L2 page tables are same size.
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#endif
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/* Since pmd_t arrays and pte_t arrays are the same size, just use casts. */
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static inline pmd_t *alloc_pmd(void)
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{
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return (pmd_t *)alloc_pte();
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}
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static inline void assign_pmd(pud_t *pud, pmd_t *pmd)
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{
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assign_pte((pmd_t *)pud, (pte_t *)pmd);
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}
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#endif /* __tilegx__ */
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/* Replace the given pmd with a full PTE table. */
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void __init shatter_pmd(pmd_t *pmd)
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{
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pte_t *pte = get_prealloc_pte(pte_pfn(*(pte_t *)pmd));
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assign_pte(pmd, pte);
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}
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#ifdef CONFIG_HIGHMEM
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/*
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* This function initializes a certain range of kernel virtual memory
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* with new bootmem page tables, everywhere page tables are missing in
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* the given range.
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*/
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/*
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* NOTE: The pagetables are allocated contiguous on the physical space
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* so we can cache the place of the first one and move around without
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* checking the pgd every time.
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*/
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static void __init page_table_range_init(unsigned long start,
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unsigned long end, pgd_t *pgd_base)
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{
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pgd_t *pgd;
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int pgd_idx;
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unsigned long vaddr;
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vaddr = start;
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pgd_idx = pgd_index(vaddr);
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pgd = pgd_base + pgd_idx;
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for ( ; (pgd_idx < PTRS_PER_PGD) && (vaddr != end); pgd++, pgd_idx++) {
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pmd_t *pmd = pmd_offset(pud_offset(pgd, vaddr), vaddr);
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if (pmd_none(*pmd))
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assign_pte(pmd, alloc_pte());
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vaddr += PMD_SIZE;
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}
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}
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#endif /* CONFIG_HIGHMEM */
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#if CHIP_HAS_CBOX_HOME_MAP()
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static int __initdata ktext_hash = 1; /* .text pages */
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static int __initdata kdata_hash = 1; /* .data and .bss pages */
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int __write_once hash_default = 1; /* kernel allocator pages */
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EXPORT_SYMBOL(hash_default);
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int __write_once kstack_hash = 1; /* if no homecaching, use h4h */
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#endif /* CHIP_HAS_CBOX_HOME_MAP */
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/*
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* CPUs to use to for striping the pages of kernel data. If hash-for-home
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* is available, this is only relevant if kcache_hash sets up the
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* .data and .bss to be page-homed, and we don't want the default mode
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* of using the full set of kernel cpus for the striping.
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*/
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static __initdata struct cpumask kdata_mask;
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static __initdata int kdata_arg_seen;
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int __write_once kdata_huge; /* if no homecaching, small pages */
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/* Combine a generic pgprot_t with cache home to get a cache-aware pgprot. */
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static pgprot_t __init construct_pgprot(pgprot_t prot, int home)
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{
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prot = pte_set_home(prot, home);
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#if CHIP_HAS_CBOX_HOME_MAP()
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if (home == PAGE_HOME_IMMUTABLE) {
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if (ktext_hash)
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prot = hv_pte_set_mode(prot, HV_PTE_MODE_CACHE_HASH_L3);
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else
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prot = hv_pte_set_mode(prot, HV_PTE_MODE_CACHE_NO_L3);
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}
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#endif
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return prot;
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}
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/*
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* For a given kernel data VA, how should it be cached?
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* We return the complete pgprot_t with caching bits set.
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*/
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static pgprot_t __init init_pgprot(ulong address)
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{
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int cpu;
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unsigned long page;
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enum { CODE_DELTA = MEM_SV_INTRPT - PAGE_OFFSET };
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#if CHIP_HAS_CBOX_HOME_MAP()
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/* For kdata=huge, everything is just hash-for-home. */
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if (kdata_huge)
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return construct_pgprot(PAGE_KERNEL, PAGE_HOME_HASH);
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#endif
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/* We map the aliased pages of permanent text inaccessible. */
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if (address < (ulong) _sinittext - CODE_DELTA)
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return PAGE_NONE;
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/*
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* We map read-only data non-coherent for performance. We could
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* use neighborhood caching on TILE64, but it's not clear it's a win.
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*/
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if ((address >= (ulong) __start_rodata &&
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address < (ulong) __end_rodata) ||
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address == (ulong) empty_zero_page) {
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return construct_pgprot(PAGE_KERNEL_RO, PAGE_HOME_IMMUTABLE);
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}
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/* As a performance optimization, keep the boot init stack here. */
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if (address >= (ulong)&init_thread_union &&
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address < (ulong)&init_thread_union + THREAD_SIZE)
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return construct_pgprot(PAGE_KERNEL, smp_processor_id());
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#ifndef __tilegx__
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#if !ATOMIC_LOCKS_FOUND_VIA_TABLE()
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/* Force the atomic_locks[] array page to be hash-for-home. */
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if (address == (ulong) atomic_locks)
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return construct_pgprot(PAGE_KERNEL, PAGE_HOME_HASH);
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#endif
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#endif
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/*
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* Everything else that isn't data or bss is heap, so mark it
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* with the initial heap home (hash-for-home, or this cpu). This
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* includes any addresses after the loaded image and any address before
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* _einitdata, since we already captured the case of text before
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* _sinittext, and __pa(einittext) is approximately __pa(sinitdata).
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*
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* All the LOWMEM pages that we mark this way will get their
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* struct page homecache properly marked later, in set_page_homes().
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* The HIGHMEM pages we leave with a default zero for their
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* homes, but with a zero free_time we don't have to actually
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* do a flush action the first time we use them, either.
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*/
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if (address >= (ulong) _end || address < (ulong) _einitdata)
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return construct_pgprot(PAGE_KERNEL, initial_heap_home());
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#if CHIP_HAS_CBOX_HOME_MAP()
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/* Use hash-for-home if requested for data/bss. */
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if (kdata_hash)
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return construct_pgprot(PAGE_KERNEL, PAGE_HOME_HASH);
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#endif
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/*
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* Make the w1data homed like heap to start with, to avoid
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* making it part of the page-striped data area when we're just
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* going to convert it to read-only soon anyway.
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*/
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if (address >= (ulong)__w1data_begin && address < (ulong)__w1data_end)
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return construct_pgprot(PAGE_KERNEL, initial_heap_home());
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/*
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* Otherwise we just hand out consecutive cpus. To avoid
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* requiring this function to hold state, we just walk forward from
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* _sdata by PAGE_SIZE, skipping the readonly and init data, to reach
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* the requested address, while walking cpu home around kdata_mask.
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* This is typically no more than a dozen or so iterations.
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*/
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page = (((ulong)__w1data_end) + PAGE_SIZE - 1) & PAGE_MASK;
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BUG_ON(address < page || address >= (ulong)_end);
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cpu = cpumask_first(&kdata_mask);
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for (; page < address; page += PAGE_SIZE) {
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if (page >= (ulong)&init_thread_union &&
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page < (ulong)&init_thread_union + THREAD_SIZE)
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continue;
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if (page == (ulong)empty_zero_page)
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continue;
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#ifndef __tilegx__
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#if !ATOMIC_LOCKS_FOUND_VIA_TABLE()
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if (page == (ulong)atomic_locks)
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continue;
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#endif
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#endif
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cpu = cpumask_next(cpu, &kdata_mask);
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if (cpu == NR_CPUS)
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cpu = cpumask_first(&kdata_mask);
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}
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return construct_pgprot(PAGE_KERNEL, cpu);
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}
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/*
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* This function sets up how we cache the kernel text. If we have
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* hash-for-home support, normally that is used instead (see the
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* kcache_hash boot flag for more information). But if we end up
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* using a page-based caching technique, this option sets up the
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* details of that. In addition, the "ktext=nocache" option may
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* always be used to disable local caching of text pages, if desired.
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*/
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static int __initdata ktext_arg_seen;
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static int __initdata ktext_small;
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static int __initdata ktext_local;
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static int __initdata ktext_all;
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static int __initdata ktext_nondataplane;
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static int __initdata ktext_nocache;
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static struct cpumask __initdata ktext_mask;
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static int __init setup_ktext(char *str)
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{
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if (str == NULL)
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return -EINVAL;
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/* If you have a leading "nocache", turn off ktext caching */
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if (strncmp(str, "nocache", 7) == 0) {
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ktext_nocache = 1;
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pr_info("ktext: disabling local caching of kernel text\n");
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str += 7;
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if (*str == ',')
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++str;
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if (*str == '\0')
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return 0;
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}
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ktext_arg_seen = 1;
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/* Default setting on Tile64: use a huge page */
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if (strcmp(str, "huge") == 0)
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pr_info("ktext: using one huge locally cached page\n");
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/* Pay TLB cost but get no cache benefit: cache small pages locally */
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else if (strcmp(str, "local") == 0) {
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ktext_small = 1;
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ktext_local = 1;
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pr_info("ktext: using small pages with local caching\n");
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}
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/* Neighborhood cache ktext pages on all cpus. */
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else if (strcmp(str, "all") == 0) {
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ktext_small = 1;
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ktext_all = 1;
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pr_info("ktext: using maximal caching neighborhood\n");
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}
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/* Neighborhood ktext pages on specified mask */
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else if (cpulist_parse(str, &ktext_mask) == 0) {
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char buf[NR_CPUS * 5];
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cpulist_scnprintf(buf, sizeof(buf), &ktext_mask);
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if (cpumask_weight(&ktext_mask) > 1) {
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ktext_small = 1;
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pr_info("ktext: using caching neighborhood %s "
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"with small pages\n", buf);
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} else {
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pr_info("ktext: caching on cpu %s with one huge page\n",
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buf);
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}
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}
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else if (*str)
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return -EINVAL;
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return 0;
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}
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early_param("ktext", setup_ktext);
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static inline pgprot_t ktext_set_nocache(pgprot_t prot)
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{
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if (!ktext_nocache)
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prot = hv_pte_set_nc(prot);
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#if CHIP_HAS_NC_AND_NOALLOC_BITS()
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else
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prot = hv_pte_set_no_alloc_l2(prot);
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#endif
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return prot;
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}
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#ifndef __tilegx__
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static pmd_t *__init get_pmd(pgd_t pgtables[], unsigned long va)
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{
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return pmd_offset(pud_offset(&pgtables[pgd_index(va)], va), va);
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}
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#else
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static pmd_t *__init get_pmd(pgd_t pgtables[], unsigned long va)
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{
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pud_t *pud = pud_offset(&pgtables[pgd_index(va)], va);
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if (pud_none(*pud))
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assign_pmd(pud, alloc_pmd());
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return pmd_offset(pud, va);
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}
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#endif
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/* Temporary page table we use for staging. */
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static pgd_t pgtables[PTRS_PER_PGD]
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__attribute__((section(".init.page")));
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/*
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* This maps the physical memory to kernel virtual address space, a total
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* of max_low_pfn pages, by creating page tables starting from address
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* PAGE_OFFSET.
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*
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* This routine transitions us from using a set of compiled-in large
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* pages to using some more precise caching, including removing access
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* to code pages mapped at PAGE_OFFSET (executed only at MEM_SV_START)
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* marking read-only data as locally cacheable, striping the remaining
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* .data and .bss across all the available tiles, and removing access
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* to pages above the top of RAM (thus ensuring a page fault from a bad
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* virtual address rather than a hypervisor shoot down for accessing
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* memory outside the assigned limits).
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*/
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static void __init kernel_physical_mapping_init(pgd_t *pgd_base)
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{
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unsigned long address, pfn;
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pmd_t *pmd;
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pte_t *pte;
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int pte_ofs;
|
|
const struct cpumask *my_cpu_mask = cpumask_of(smp_processor_id());
|
|
struct cpumask kstripe_mask;
|
|
int rc, i;
|
|
|
|
#if CHIP_HAS_CBOX_HOME_MAP()
|
|
if (ktext_arg_seen && ktext_hash) {
|
|
pr_warning("warning: \"ktext\" boot argument ignored"
|
|
" if \"kcache_hash\" sets up text hash-for-home\n");
|
|
ktext_small = 0;
|
|
}
|
|
|
|
if (kdata_arg_seen && kdata_hash) {
|
|
pr_warning("warning: \"kdata\" boot argument ignored"
|
|
" if \"kcache_hash\" sets up data hash-for-home\n");
|
|
}
|
|
|
|
if (kdata_huge && !hash_default) {
|
|
pr_warning("warning: disabling \"kdata=huge\"; requires"
|
|
" kcache_hash=all or =allbutstack\n");
|
|
kdata_huge = 0;
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Set up a mask for cpus to use for kernel striping.
|
|
* This is normally all cpus, but minus dataplane cpus if any.
|
|
* If the dataplane covers the whole chip, we stripe over
|
|
* the whole chip too.
|
|
*/
|
|
cpumask_copy(&kstripe_mask, cpu_possible_mask);
|
|
if (!kdata_arg_seen)
|
|
kdata_mask = kstripe_mask;
|
|
|
|
/* Allocate and fill in L2 page tables */
|
|
for (i = 0; i < MAX_NUMNODES; ++i) {
|
|
#ifdef CONFIG_HIGHMEM
|
|
unsigned long end_pfn = node_lowmem_end_pfn[i];
|
|
#else
|
|
unsigned long end_pfn = node_end_pfn[i];
|
|
#endif
|
|
unsigned long end_huge_pfn = 0;
|
|
|
|
/* Pre-shatter the last huge page to allow per-cpu pages. */
|
|
if (kdata_huge)
|
|
end_huge_pfn = end_pfn - (HPAGE_SIZE >> PAGE_SHIFT);
|
|
|
|
pfn = node_start_pfn[i];
|
|
|
|
/* Allocate enough memory to hold L2 page tables for node. */
|
|
init_prealloc_ptes(i, end_pfn - pfn);
|
|
|
|
address = (unsigned long) pfn_to_kaddr(pfn);
|
|
while (pfn < end_pfn) {
|
|
BUG_ON(address & (HPAGE_SIZE-1));
|
|
pmd = get_pmd(pgtables, address);
|
|
pte = get_prealloc_pte(pfn);
|
|
if (pfn < end_huge_pfn) {
|
|
pgprot_t prot = init_pgprot(address);
|
|
*(pte_t *)pmd = pte_mkhuge(pfn_pte(pfn, prot));
|
|
for (pte_ofs = 0; pte_ofs < PTRS_PER_PTE;
|
|
pfn++, pte_ofs++, address += PAGE_SIZE)
|
|
pte[pte_ofs] = pfn_pte(pfn, prot);
|
|
} else {
|
|
if (kdata_huge)
|
|
printk(KERN_DEBUG "pre-shattered huge"
|
|
" page at %#lx\n", address);
|
|
for (pte_ofs = 0; pte_ofs < PTRS_PER_PTE;
|
|
pfn++, pte_ofs++, address += PAGE_SIZE) {
|
|
pgprot_t prot = init_pgprot(address);
|
|
pte[pte_ofs] = pfn_pte(pfn, prot);
|
|
}
|
|
assign_pte(pmd, pte);
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Set or check ktext_map now that we have cpu_possible_mask
|
|
* and kstripe_mask to work with.
|
|
*/
|
|
if (ktext_all)
|
|
cpumask_copy(&ktext_mask, cpu_possible_mask);
|
|
else if (ktext_nondataplane)
|
|
ktext_mask = kstripe_mask;
|
|
else if (!cpumask_empty(&ktext_mask)) {
|
|
/* Sanity-check any mask that was requested */
|
|
struct cpumask bad;
|
|
cpumask_andnot(&bad, &ktext_mask, cpu_possible_mask);
|
|
cpumask_and(&ktext_mask, &ktext_mask, cpu_possible_mask);
|
|
if (!cpumask_empty(&bad)) {
|
|
char buf[NR_CPUS * 5];
|
|
cpulist_scnprintf(buf, sizeof(buf), &bad);
|
|
pr_info("ktext: not using unavailable cpus %s\n", buf);
|
|
}
|
|
if (cpumask_empty(&ktext_mask)) {
|
|
pr_warning("ktext: no valid cpus; caching on %d.\n",
|
|
smp_processor_id());
|
|
cpumask_copy(&ktext_mask,
|
|
cpumask_of(smp_processor_id()));
|
|
}
|
|
}
|
|
|
|
address = MEM_SV_INTRPT;
|
|
pmd = get_pmd(pgtables, address);
|
|
if (ktext_small) {
|
|
/* Allocate an L2 PTE for the kernel text */
|
|
int cpu = 0;
|
|
pgprot_t prot = construct_pgprot(PAGE_KERNEL_EXEC,
|
|
PAGE_HOME_IMMUTABLE);
|
|
|
|
if (ktext_local) {
|
|
if (ktext_nocache)
|
|
prot = hv_pte_set_mode(prot,
|
|
HV_PTE_MODE_UNCACHED);
|
|
else
|
|
prot = hv_pte_set_mode(prot,
|
|
HV_PTE_MODE_CACHE_NO_L3);
|
|
} else {
|
|
prot = hv_pte_set_mode(prot,
|
|
HV_PTE_MODE_CACHE_TILE_L3);
|
|
cpu = cpumask_first(&ktext_mask);
|
|
|
|
prot = ktext_set_nocache(prot);
|
|
}
|
|
|
|
BUG_ON(address != (unsigned long)_stext);
|
|
pfn = 0; /* code starts at PA 0 */
|
|
pte = alloc_pte();
|
|
for (pte_ofs = 0; address < (unsigned long)_einittext;
|
|
pfn++, pte_ofs++, address += PAGE_SIZE) {
|
|
if (!ktext_local) {
|
|
prot = set_remote_cache_cpu(prot, cpu);
|
|
cpu = cpumask_next(cpu, &ktext_mask);
|
|
if (cpu == NR_CPUS)
|
|
cpu = cpumask_first(&ktext_mask);
|
|
}
|
|
pte[pte_ofs] = pfn_pte(pfn, prot);
|
|
}
|
|
assign_pte(pmd, pte);
|
|
} else {
|
|
pte_t pteval = pfn_pte(0, PAGE_KERNEL_EXEC);
|
|
pteval = pte_mkhuge(pteval);
|
|
#if CHIP_HAS_CBOX_HOME_MAP()
|
|
if (ktext_hash) {
|
|
pteval = hv_pte_set_mode(pteval,
|
|
HV_PTE_MODE_CACHE_HASH_L3);
|
|
pteval = ktext_set_nocache(pteval);
|
|
} else
|
|
#endif /* CHIP_HAS_CBOX_HOME_MAP() */
|
|
if (cpumask_weight(&ktext_mask) == 1) {
|
|
pteval = set_remote_cache_cpu(pteval,
|
|
cpumask_first(&ktext_mask));
|
|
pteval = hv_pte_set_mode(pteval,
|
|
HV_PTE_MODE_CACHE_TILE_L3);
|
|
pteval = ktext_set_nocache(pteval);
|
|
} else if (ktext_nocache)
|
|
pteval = hv_pte_set_mode(pteval,
|
|
HV_PTE_MODE_UNCACHED);
|
|
else
|
|
pteval = hv_pte_set_mode(pteval,
|
|
HV_PTE_MODE_CACHE_NO_L3);
|
|
*(pte_t *)pmd = pteval;
|
|
}
|
|
|
|
/* Set swapper_pgprot here so it is flushed to memory right away. */
|
|
swapper_pgprot = init_pgprot((unsigned long)swapper_pg_dir);
|
|
|
|
/*
|
|
* Since we may be changing the caching of the stack and page
|
|
* table itself, we invoke an assembly helper to do the
|
|
* following steps:
|
|
*
|
|
* - flush the cache so we start with an empty slate
|
|
* - install pgtables[] as the real page table
|
|
* - flush the TLB so the new page table takes effect
|
|
*/
|
|
rc = flush_and_install_context(__pa(pgtables),
|
|
init_pgprot((unsigned long)pgtables),
|
|
__get_cpu_var(current_asid),
|
|
cpumask_bits(my_cpu_mask));
|
|
BUG_ON(rc != 0);
|
|
|
|
/* Copy the page table back to the normal swapper_pg_dir. */
|
|
memcpy(pgd_base, pgtables, sizeof(pgtables));
|
|
__install_page_table(pgd_base, __get_cpu_var(current_asid),
|
|
swapper_pgprot);
|
|
}
|
|
|
|
/*
|
|
* devmem_is_allowed() checks to see if /dev/mem access to a certain address
|
|
* is valid. The argument is a physical page number.
|
|
*
|
|
* On Tile, the only valid things for which we can just hand out unchecked
|
|
* PTEs are the kernel code and data. Anything else might change its
|
|
* homing with time, and we wouldn't know to adjust the /dev/mem PTEs.
|
|
* Note that init_thread_union is released to heap soon after boot,
|
|
* so we include it in the init data.
|
|
*
|
|
* For TILE-Gx, we might want to consider allowing access to PA
|
|
* regions corresponding to PCI space, etc.
|
|
*/
|
|
int devmem_is_allowed(unsigned long pagenr)
|
|
{
|
|
return pagenr < kaddr_to_pfn(_end) &&
|
|
!(pagenr >= kaddr_to_pfn(&init_thread_union) ||
|
|
pagenr < kaddr_to_pfn(_einitdata)) &&
|
|
!(pagenr >= kaddr_to_pfn(_sinittext) ||
|
|
pagenr <= kaddr_to_pfn(_einittext-1));
|
|
}
|
|
|
|
#ifdef CONFIG_HIGHMEM
|
|
static void __init permanent_kmaps_init(pgd_t *pgd_base)
|
|
{
|
|
pgd_t *pgd;
|
|
pud_t *pud;
|
|
pmd_t *pmd;
|
|
pte_t *pte;
|
|
unsigned long vaddr;
|
|
|
|
vaddr = PKMAP_BASE;
|
|
page_table_range_init(vaddr, vaddr + PAGE_SIZE*LAST_PKMAP, pgd_base);
|
|
|
|
pgd = swapper_pg_dir + pgd_index(vaddr);
|
|
pud = pud_offset(pgd, vaddr);
|
|
pmd = pmd_offset(pud, vaddr);
|
|
pte = pte_offset_kernel(pmd, vaddr);
|
|
pkmap_page_table = pte;
|
|
}
|
|
#endif /* CONFIG_HIGHMEM */
|
|
|
|
|
|
static void __init init_free_pfn_range(unsigned long start, unsigned long end)
|
|
{
|
|
unsigned long pfn;
|
|
struct page *page = pfn_to_page(start);
|
|
|
|
for (pfn = start; pfn < end; ) {
|
|
/* Optimize by freeing pages in large batches */
|
|
int order = __ffs(pfn);
|
|
int count, i;
|
|
struct page *p;
|
|
|
|
if (order >= MAX_ORDER)
|
|
order = MAX_ORDER-1;
|
|
count = 1 << order;
|
|
while (pfn + count > end) {
|
|
count >>= 1;
|
|
--order;
|
|
}
|
|
for (p = page, i = 0; i < count; ++i, ++p) {
|
|
__ClearPageReserved(p);
|
|
/*
|
|
* Hacky direct set to avoid unnecessary
|
|
* lock take/release for EVERY page here.
|
|
*/
|
|
p->_count.counter = 0;
|
|
p->_mapcount.counter = -1;
|
|
}
|
|
init_page_count(page);
|
|
__free_pages(page, order);
|
|
totalram_pages += count;
|
|
|
|
page += count;
|
|
pfn += count;
|
|
}
|
|
}
|
|
|
|
static void __init set_non_bootmem_pages_init(void)
|
|
{
|
|
struct zone *z;
|
|
for_each_zone(z) {
|
|
unsigned long start, end;
|
|
int nid = z->zone_pgdat->node_id;
|
|
int idx = zone_idx(z);
|
|
|
|
start = z->zone_start_pfn;
|
|
if (start == 0)
|
|
continue; /* bootmem */
|
|
end = start + z->spanned_pages;
|
|
if (idx == ZONE_NORMAL) {
|
|
BUG_ON(start != node_start_pfn[nid]);
|
|
start = node_free_pfn[nid];
|
|
}
|
|
#ifdef CONFIG_HIGHMEM
|
|
if (idx == ZONE_HIGHMEM)
|
|
totalhigh_pages += z->spanned_pages;
|
|
#endif
|
|
if (kdata_huge) {
|
|
unsigned long percpu_pfn = node_percpu_pfn[nid];
|
|
if (start < percpu_pfn && end > percpu_pfn)
|
|
end = percpu_pfn;
|
|
}
|
|
#ifdef CONFIG_PCI
|
|
if (start <= pci_reserve_start_pfn &&
|
|
end > pci_reserve_start_pfn) {
|
|
if (end > pci_reserve_end_pfn)
|
|
init_free_pfn_range(pci_reserve_end_pfn, end);
|
|
end = pci_reserve_start_pfn;
|
|
}
|
|
#endif
|
|
init_free_pfn_range(start, end);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* paging_init() sets up the page tables - note that all of lowmem is
|
|
* already mapped by head.S.
|
|
*/
|
|
void __init paging_init(void)
|
|
{
|
|
#ifdef CONFIG_HIGHMEM
|
|
unsigned long vaddr, end;
|
|
#endif
|
|
#ifdef __tilegx__
|
|
pud_t *pud;
|
|
#endif
|
|
pgd_t *pgd_base = swapper_pg_dir;
|
|
|
|
kernel_physical_mapping_init(pgd_base);
|
|
|
|
#ifdef CONFIG_HIGHMEM
|
|
/*
|
|
* Fixed mappings, only the page table structure has to be
|
|
* created - mappings will be set by set_fixmap():
|
|
*/
|
|
vaddr = __fix_to_virt(__end_of_fixed_addresses - 1) & PMD_MASK;
|
|
end = (FIXADDR_TOP + PMD_SIZE - 1) & PMD_MASK;
|
|
page_table_range_init(vaddr, end, pgd_base);
|
|
permanent_kmaps_init(pgd_base);
|
|
#endif
|
|
|
|
#ifdef __tilegx__
|
|
/*
|
|
* Since GX allocates just one pmd_t array worth of vmalloc space,
|
|
* we go ahead and allocate it statically here, then share it
|
|
* globally. As a result we don't have to worry about any task
|
|
* changing init_mm once we get up and running, and there's no
|
|
* need for e.g. vmalloc_sync_all().
|
|
*/
|
|
BUILD_BUG_ON(pgd_index(VMALLOC_START) != pgd_index(VMALLOC_END));
|
|
pud = pud_offset(pgd_base + pgd_index(VMALLOC_START), VMALLOC_START);
|
|
assign_pmd(pud, alloc_pmd());
|
|
#endif
|
|
}
|
|
|
|
|
|
/*
|
|
* Walk the kernel page tables and derive the page_home() from
|
|
* the PTEs, so that set_pte() can properly validate the caching
|
|
* of all PTEs it sees.
|
|
*/
|
|
void __init set_page_homes(void)
|
|
{
|
|
}
|
|
|
|
static void __init set_max_mapnr_init(void)
|
|
{
|
|
#ifdef CONFIG_FLATMEM
|
|
max_mapnr = max_low_pfn;
|
|
#endif
|
|
}
|
|
|
|
void __init mem_init(void)
|
|
{
|
|
int codesize, datasize, initsize;
|
|
int i;
|
|
#ifndef __tilegx__
|
|
void *last;
|
|
#endif
|
|
|
|
#ifdef CONFIG_FLATMEM
|
|
if (!mem_map)
|
|
BUG();
|
|
#endif
|
|
|
|
#ifdef CONFIG_HIGHMEM
|
|
/* check that fixmap and pkmap do not overlap */
|
|
if (PKMAP_ADDR(LAST_PKMAP-1) >= FIXADDR_START) {
|
|
pr_err("fixmap and kmap areas overlap"
|
|
" - this will crash\n");
|
|
pr_err("pkstart: %lxh pkend: %lxh fixstart %lxh\n",
|
|
PKMAP_BASE, PKMAP_ADDR(LAST_PKMAP-1),
|
|
FIXADDR_START);
|
|
BUG();
|
|
}
|
|
#endif
|
|
|
|
set_max_mapnr_init();
|
|
|
|
/* this will put all bootmem onto the freelists */
|
|
totalram_pages += free_all_bootmem();
|
|
|
|
/* count all remaining LOWMEM and give all HIGHMEM to page allocator */
|
|
set_non_bootmem_pages_init();
|
|
|
|
codesize = (unsigned long)&_etext - (unsigned long)&_text;
|
|
datasize = (unsigned long)&_end - (unsigned long)&_sdata;
|
|
initsize = (unsigned long)&_einittext - (unsigned long)&_sinittext;
|
|
initsize += (unsigned long)&_einitdata - (unsigned long)&_sinitdata;
|
|
|
|
pr_info("Memory: %luk/%luk available (%dk kernel code, %dk data, %dk init, %ldk highmem)\n",
|
|
(unsigned long) nr_free_pages() << (PAGE_SHIFT-10),
|
|
num_physpages << (PAGE_SHIFT-10),
|
|
codesize >> 10,
|
|
datasize >> 10,
|
|
initsize >> 10,
|
|
(unsigned long) (totalhigh_pages << (PAGE_SHIFT-10))
|
|
);
|
|
|
|
/*
|
|
* In debug mode, dump some interesting memory mappings.
|
|
*/
|
|
#ifdef CONFIG_HIGHMEM
|
|
printk(KERN_DEBUG " KMAP %#lx - %#lx\n",
|
|
FIXADDR_START, FIXADDR_TOP + PAGE_SIZE - 1);
|
|
printk(KERN_DEBUG " PKMAP %#lx - %#lx\n",
|
|
PKMAP_BASE, PKMAP_ADDR(LAST_PKMAP) - 1);
|
|
#endif
|
|
#ifdef CONFIG_HUGEVMAP
|
|
printk(KERN_DEBUG " HUGEMAP %#lx - %#lx\n",
|
|
HUGE_VMAP_BASE, HUGE_VMAP_END - 1);
|
|
#endif
|
|
printk(KERN_DEBUG " VMALLOC %#lx - %#lx\n",
|
|
_VMALLOC_START, _VMALLOC_END - 1);
|
|
#ifdef __tilegx__
|
|
for (i = MAX_NUMNODES-1; i >= 0; --i) {
|
|
struct pglist_data *node = &node_data[i];
|
|
if (node->node_present_pages) {
|
|
unsigned long start = (unsigned long)
|
|
pfn_to_kaddr(node->node_start_pfn);
|
|
unsigned long end = start +
|
|
(node->node_present_pages << PAGE_SHIFT);
|
|
printk(KERN_DEBUG " MEM%d %#lx - %#lx\n",
|
|
i, start, end - 1);
|
|
}
|
|
}
|
|
#else
|
|
last = high_memory;
|
|
for (i = MAX_NUMNODES-1; i >= 0; --i) {
|
|
if ((unsigned long)vbase_map[i] != -1UL) {
|
|
printk(KERN_DEBUG " LOWMEM%d %#lx - %#lx\n",
|
|
i, (unsigned long) (vbase_map[i]),
|
|
(unsigned long) (last-1));
|
|
last = vbase_map[i];
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#ifndef __tilegx__
|
|
/*
|
|
* Convert from using one lock for all atomic operations to
|
|
* one per cpu.
|
|
*/
|
|
__init_atomic_per_cpu();
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* this is for the non-NUMA, single node SMP system case.
|
|
* Specifically, in the case of x86, we will always add
|
|
* memory to the highmem for now.
|
|
*/
|
|
#ifndef CONFIG_NEED_MULTIPLE_NODES
|
|
int arch_add_memory(u64 start, u64 size)
|
|
{
|
|
struct pglist_data *pgdata = &contig_page_data;
|
|
struct zone *zone = pgdata->node_zones + MAX_NR_ZONES-1;
|
|
unsigned long start_pfn = start >> PAGE_SHIFT;
|
|
unsigned long nr_pages = size >> PAGE_SHIFT;
|
|
|
|
return __add_pages(zone, start_pfn, nr_pages);
|
|
}
|
|
|
|
int remove_memory(u64 start, u64 size)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
#endif
|
|
|
|
struct kmem_cache *pgd_cache;
|
|
|
|
void __init pgtable_cache_init(void)
|
|
{
|
|
pgd_cache = kmem_cache_create("pgd",
|
|
PTRS_PER_PGD*sizeof(pgd_t),
|
|
PTRS_PER_PGD*sizeof(pgd_t),
|
|
0,
|
|
NULL);
|
|
if (!pgd_cache)
|
|
panic("pgtable_cache_init(): Cannot create pgd cache");
|
|
}
|
|
|
|
#if !CHIP_HAS_COHERENT_LOCAL_CACHE()
|
|
/*
|
|
* The __w1data area holds data that is only written during initialization,
|
|
* and is read-only and thus freely cacheable thereafter. Fix the page
|
|
* table entries that cover that region accordingly.
|
|
*/
|
|
static void mark_w1data_ro(void)
|
|
{
|
|
/* Loop over page table entries */
|
|
unsigned long addr = (unsigned long)__w1data_begin;
|
|
BUG_ON((addr & (PAGE_SIZE-1)) != 0);
|
|
for (; addr <= (unsigned long)__w1data_end - 1; addr += PAGE_SIZE) {
|
|
unsigned long pfn = kaddr_to_pfn((void *)addr);
|
|
pte_t *ptep = virt_to_pte(NULL, addr);
|
|
BUG_ON(pte_huge(*ptep)); /* not relevant for kdata_huge */
|
|
set_pte_at(&init_mm, addr, ptep, pfn_pte(pfn, PAGE_KERNEL_RO));
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_DEBUG_PAGEALLOC
|
|
static long __write_once initfree;
|
|
#else
|
|
static long __write_once initfree = 1;
|
|
#endif
|
|
|
|
/* Select whether to free (1) or mark unusable (0) the __init pages. */
|
|
static int __init set_initfree(char *str)
|
|
{
|
|
strict_strtol(str, 0, &initfree);
|
|
pr_info("initfree: %s free init pages\n", initfree ? "will" : "won't");
|
|
return 1;
|
|
}
|
|
__setup("initfree=", set_initfree);
|
|
|
|
static void free_init_pages(char *what, unsigned long begin, unsigned long end)
|
|
{
|
|
unsigned long addr = (unsigned long) begin;
|
|
|
|
if (kdata_huge && !initfree) {
|
|
pr_warning("Warning: ignoring initfree=0:"
|
|
" incompatible with kdata=huge\n");
|
|
initfree = 1;
|
|
}
|
|
end = (end + PAGE_SIZE - 1) & PAGE_MASK;
|
|
local_flush_tlb_pages(NULL, begin, PAGE_SIZE, end - begin);
|
|
for (addr = begin; addr < end; addr += PAGE_SIZE) {
|
|
/*
|
|
* Note we just reset the home here directly in the
|
|
* page table. We know this is safe because our caller
|
|
* just flushed the caches on all the other cpus,
|
|
* and they won't be touching any of these pages.
|
|
*/
|
|
int pfn = kaddr_to_pfn((void *)addr);
|
|
struct page *page = pfn_to_page(pfn);
|
|
pte_t *ptep = virt_to_pte(NULL, addr);
|
|
if (!initfree) {
|
|
/*
|
|
* If debugging page accesses then do not free
|
|
* this memory but mark them not present - any
|
|
* buggy init-section access will create a
|
|
* kernel page fault:
|
|
*/
|
|
pte_clear(&init_mm, addr, ptep);
|
|
continue;
|
|
}
|
|
__ClearPageReserved(page);
|
|
init_page_count(page);
|
|
if (pte_huge(*ptep))
|
|
BUG_ON(!kdata_huge);
|
|
else
|
|
set_pte_at(&init_mm, addr, ptep,
|
|
pfn_pte(pfn, PAGE_KERNEL));
|
|
memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
|
|
free_page(addr);
|
|
totalram_pages++;
|
|
}
|
|
pr_info("Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
|
|
}
|
|
|
|
void free_initmem(void)
|
|
{
|
|
const unsigned long text_delta = MEM_SV_INTRPT - PAGE_OFFSET;
|
|
|
|
/*
|
|
* Evict the dirty initdata on the boot cpu, evict the w1data
|
|
* wherever it's homed, and evict all the init code everywhere.
|
|
* We are guaranteed that no one will touch the init pages any
|
|
* more, and although other cpus may be touching the w1data,
|
|
* we only actually change the caching on tile64, which won't
|
|
* be keeping local copies in the other tiles' caches anyway.
|
|
*/
|
|
homecache_evict(&cpu_cacheable_map);
|
|
|
|
/* Free the data pages that we won't use again after init. */
|
|
free_init_pages("unused kernel data",
|
|
(unsigned long)_sinitdata,
|
|
(unsigned long)_einitdata);
|
|
|
|
/*
|
|
* Free the pages mapped from 0xc0000000 that correspond to code
|
|
* pages from MEM_SV_INTRPT that we won't use again after init.
|
|
*/
|
|
free_init_pages("unused kernel text",
|
|
(unsigned long)_sinittext - text_delta,
|
|
(unsigned long)_einittext - text_delta);
|
|
|
|
#if !CHIP_HAS_COHERENT_LOCAL_CACHE()
|
|
/*
|
|
* Upgrade the .w1data section to globally cached.
|
|
* We don't do this on tilepro, since the cache architecture
|
|
* pretty much makes it irrelevant, and in any case we end
|
|
* up having racing issues with other tiles that may touch
|
|
* the data after we flush the cache but before we update
|
|
* the PTEs and flush the TLBs, causing sharer shootdowns
|
|
* later. Even though this is to clean data, it seems like
|
|
* an unnecessary complication.
|
|
*/
|
|
mark_w1data_ro();
|
|
#endif
|
|
|
|
/* Do a global TLB flush so everyone sees the changes. */
|
|
flush_tlb_all();
|
|
}
|