forked from Minki/linux
6dad4e8ab3
register xfrmdev_ops callbacks, Send IPsec tunneled data to HW for inline processing. The driver use hardware crypto accelerator to encrypt and generate ICV for the transmitted packet in Inline mode. Signed-off-by: Atul Gupta <atul.gupta@chelsio.com> Signed-off-by: Harsh Jain <harsh@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
661 lines
18 KiB
C
661 lines
18 KiB
C
/*
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* This file is part of the Chelsio T6 Crypto driver for Linux.
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*
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* Copyright (c) 2003-2017 Chelsio Communications, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Written and Maintained by:
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* Atul Gupta (atul.gupta@chelsio.com)
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*/
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#define pr_fmt(fmt) "chcr:" fmt
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/crypto.h>
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#include <linux/cryptohash.h>
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#include <linux/skbuff.h>
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#include <linux/rtnetlink.h>
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#include <linux/highmem.h>
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#include <linux/if_vlan.h>
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#include <linux/ip.h>
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#include <linux/netdevice.h>
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#include <net/esp.h>
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#include <net/xfrm.h>
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#include <crypto/aes.h>
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#include <crypto/algapi.h>
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#include <crypto/hash.h>
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#include <crypto/sha.h>
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#include <crypto/authenc.h>
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#include <crypto/internal/aead.h>
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#include <crypto/null.h>
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#include <crypto/internal/skcipher.h>
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#include <crypto/aead.h>
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#include <crypto/scatterwalk.h>
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#include <crypto/internal/hash.h>
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#include "chcr_core.h"
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#include "chcr_algo.h"
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#include "chcr_crypto.h"
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/*
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* Max Tx descriptor space we allow for an Ethernet packet to be inlined
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* into a WR.
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*/
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#define MAX_IMM_TX_PKT_LEN 256
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#define GCM_ESP_IV_SIZE 8
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static int chcr_xfrm_add_state(struct xfrm_state *x);
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static void chcr_xfrm_del_state(struct xfrm_state *x);
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static void chcr_xfrm_free_state(struct xfrm_state *x);
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static bool chcr_ipsec_offload_ok(struct sk_buff *skb, struct xfrm_state *x);
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static const struct xfrmdev_ops chcr_xfrmdev_ops = {
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.xdo_dev_state_add = chcr_xfrm_add_state,
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.xdo_dev_state_delete = chcr_xfrm_del_state,
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.xdo_dev_state_free = chcr_xfrm_free_state,
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.xdo_dev_offload_ok = chcr_ipsec_offload_ok,
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};
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/* Add offload xfrms to Chelsio Interface */
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void chcr_add_xfrmops(const struct cxgb4_lld_info *lld)
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{
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struct net_device *netdev = NULL;
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int i;
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for (i = 0; i < lld->nports; i++) {
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netdev = lld->ports[i];
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if (!netdev)
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continue;
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netdev->xfrmdev_ops = &chcr_xfrmdev_ops;
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netdev->hw_enc_features |= NETIF_F_HW_ESP;
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netdev->features |= NETIF_F_HW_ESP;
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rtnl_lock();
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netdev_change_features(netdev);
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rtnl_unlock();
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}
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}
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static inline int chcr_ipsec_setauthsize(struct xfrm_state *x,
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struct ipsec_sa_entry *sa_entry)
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{
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int hmac_ctrl;
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int authsize = x->aead->alg_icv_len / 8;
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sa_entry->authsize = authsize;
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switch (authsize) {
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case ICV_8:
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hmac_ctrl = CHCR_SCMD_HMAC_CTRL_DIV2;
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break;
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case ICV_12:
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hmac_ctrl = CHCR_SCMD_HMAC_CTRL_IPSEC_96BIT;
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break;
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case ICV_16:
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hmac_ctrl = CHCR_SCMD_HMAC_CTRL_NO_TRUNC;
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break;
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default:
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return -EINVAL;
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}
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return hmac_ctrl;
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}
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static inline int chcr_ipsec_setkey(struct xfrm_state *x,
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struct ipsec_sa_entry *sa_entry)
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{
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struct crypto_cipher *cipher;
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int keylen = (x->aead->alg_key_len + 7) / 8;
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unsigned char *key = x->aead->alg_key;
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int ck_size, key_ctx_size = 0;
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unsigned char ghash_h[AEAD_H_SIZE];
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int ret = 0;
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if (keylen > 3) {
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keylen -= 4; /* nonce/salt is present in the last 4 bytes */
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memcpy(sa_entry->salt, key + keylen, 4);
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}
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if (keylen == AES_KEYSIZE_128) {
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ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_128;
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} else if (keylen == AES_KEYSIZE_192) {
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ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_192;
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} else if (keylen == AES_KEYSIZE_256) {
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ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_256;
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} else {
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pr_err("GCM: Invalid key length %d\n", keylen);
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ret = -EINVAL;
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goto out;
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}
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memcpy(sa_entry->key, key, keylen);
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sa_entry->enckey_len = keylen;
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key_ctx_size = sizeof(struct _key_ctx) +
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((DIV_ROUND_UP(keylen, 16)) << 4) +
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AEAD_H_SIZE;
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sa_entry->key_ctx_hdr = FILL_KEY_CTX_HDR(ck_size,
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CHCR_KEYCTX_MAC_KEY_SIZE_128,
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0, 0,
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key_ctx_size >> 4);
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/* Calculate the H = CIPH(K, 0 repeated 16 times).
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* It will go in key context
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*/
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cipher = crypto_alloc_cipher("aes-generic", 0, 0);
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if (IS_ERR(cipher)) {
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sa_entry->enckey_len = 0;
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ret = -ENOMEM;
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goto out;
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}
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ret = crypto_cipher_setkey(cipher, key, keylen);
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if (ret) {
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sa_entry->enckey_len = 0;
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goto out1;
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}
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memset(ghash_h, 0, AEAD_H_SIZE);
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crypto_cipher_encrypt_one(cipher, ghash_h, ghash_h);
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memcpy(sa_entry->key + (DIV_ROUND_UP(sa_entry->enckey_len, 16) *
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16), ghash_h, AEAD_H_SIZE);
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sa_entry->kctx_len = ((DIV_ROUND_UP(sa_entry->enckey_len, 16)) << 4) +
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AEAD_H_SIZE;
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out1:
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crypto_free_cipher(cipher);
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out:
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return ret;
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}
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/*
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* chcr_xfrm_add_state
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* returns 0 on success, negative error if failed to send message to FPGA
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* positive error if FPGA returned a bad response
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*/
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static int chcr_xfrm_add_state(struct xfrm_state *x)
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{
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struct net_device *netdev = x->xso.dev;
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struct port_info *pi = netdev_priv(netdev);
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struct ipsec_sa_entry *sa_entry;
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struct adapter *adap;
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int res = 0;
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adap = pi->adapter;
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if (x->props.aalgo != SADB_AALG_NONE) {
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pr_debug("CHCR: Cannot offload authenticated xfrm states\n");
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return -EINVAL;
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}
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if (x->props.calgo != SADB_X_CALG_NONE) {
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pr_debug("CHCR: Cannot offload compressed xfrm states\n");
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return -EINVAL;
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}
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if (x->props.flags & XFRM_STATE_ESN) {
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pr_debug("CHCR: Cannot offload ESN xfrm states\n");
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return -EINVAL;
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}
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if (x->props.family != AF_INET &&
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x->props.family != AF_INET6) {
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pr_debug("CHCR: Only IPv4/6 xfrm state offloaded\n");
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return -EINVAL;
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}
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if (x->props.mode != XFRM_MODE_TRANSPORT &&
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x->props.mode != XFRM_MODE_TUNNEL) {
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pr_debug("CHCR: Only transport and tunnel xfrm offload\n");
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return -EINVAL;
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}
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if (x->id.proto != IPPROTO_ESP) {
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pr_debug("CHCR: Only ESP xfrm state offloaded\n");
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return -EINVAL;
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}
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if (x->encap) {
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pr_debug("CHCR: Encapsulated xfrm state not offloaded\n");
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return -EINVAL;
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}
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if (!x->aead) {
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pr_debug("CHCR: Cannot offload xfrm states without aead\n");
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return -EINVAL;
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}
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if (x->aead->alg_icv_len != 128 &&
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x->aead->alg_icv_len != 96) {
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pr_debug("CHCR: Cannot offload xfrm states with AEAD ICV length other than 96b & 128b\n");
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return -EINVAL;
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}
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if ((x->aead->alg_key_len != 128 + 32) &&
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(x->aead->alg_key_len != 256 + 32)) {
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pr_debug("CHCR: Cannot offload xfrm states with AEAD key length other than 128/256 bit\n");
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return -EINVAL;
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}
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if (x->tfcpad) {
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pr_debug("CHCR: Cannot offload xfrm states with tfc padding\n");
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return -EINVAL;
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}
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if (!x->geniv) {
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pr_debug("CHCR: Cannot offload xfrm states without geniv\n");
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return -EINVAL;
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}
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if (strcmp(x->geniv, "seqiv")) {
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pr_debug("CHCR: Cannot offload xfrm states with geniv other than seqiv\n");
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return -EINVAL;
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}
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sa_entry = kzalloc(sizeof(*sa_entry), GFP_KERNEL);
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if (!sa_entry) {
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res = -ENOMEM;
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goto out;
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}
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sa_entry->hmac_ctrl = chcr_ipsec_setauthsize(x, sa_entry);
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chcr_ipsec_setkey(x, sa_entry);
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x->xso.offload_handle = (unsigned long)sa_entry;
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try_module_get(THIS_MODULE);
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out:
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return res;
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}
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static void chcr_xfrm_del_state(struct xfrm_state *x)
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{
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/* do nothing */
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if (!x->xso.offload_handle)
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return;
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}
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static void chcr_xfrm_free_state(struct xfrm_state *x)
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{
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struct ipsec_sa_entry *sa_entry;
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if (!x->xso.offload_handle)
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return;
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sa_entry = (struct ipsec_sa_entry *)x->xso.offload_handle;
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kfree(sa_entry);
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module_put(THIS_MODULE);
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}
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static bool chcr_ipsec_offload_ok(struct sk_buff *skb, struct xfrm_state *x)
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{
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/* Offload with IP options is not supported yet */
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if (ip_hdr(skb)->ihl > 5)
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return false;
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return true;
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}
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static inline int is_eth_imm(const struct sk_buff *skb, unsigned int kctx_len)
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{
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int hdrlen = sizeof(struct chcr_ipsec_req) + kctx_len;
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hdrlen += sizeof(struct cpl_tx_pkt);
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if (skb->len <= MAX_IMM_TX_PKT_LEN - hdrlen)
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return hdrlen;
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return 0;
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}
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static inline unsigned int calc_tx_sec_flits(const struct sk_buff *skb,
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unsigned int kctx_len)
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{
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unsigned int flits;
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int hdrlen = is_eth_imm(skb, kctx_len);
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/* If the skb is small enough, we can pump it out as a work request
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* with only immediate data. In that case we just have to have the
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* TX Packet header plus the skb data in the Work Request.
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*/
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if (hdrlen)
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return DIV_ROUND_UP(skb->len + hdrlen, sizeof(__be64));
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flits = sgl_len(skb_shinfo(skb)->nr_frags + 1);
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/* Otherwise, we're going to have to construct a Scatter gather list
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* of the skb body and fragments. We also include the flits necessary
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* for the TX Packet Work Request and CPL. We always have a firmware
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* Write Header (incorporated as part of the cpl_tx_pkt_lso and
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* cpl_tx_pkt structures), followed by either a TX Packet Write CPL
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* message or, if we're doing a Large Send Offload, an LSO CPL message
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* with an embedded TX Packet Write CPL message.
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*/
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flits += (sizeof(struct fw_ulptx_wr) +
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sizeof(struct chcr_ipsec_req) +
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kctx_len +
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sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64);
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return flits;
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}
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inline void *copy_cpltx_pktxt(struct sk_buff *skb,
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struct net_device *dev,
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void *pos)
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{
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struct adapter *adap;
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struct port_info *pi;
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struct sge_eth_txq *q;
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struct cpl_tx_pkt_core *cpl;
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u64 cntrl;
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u32 ctrl0, qidx;
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pi = netdev_priv(dev);
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adap = pi->adapter;
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qidx = skb->queue_mapping;
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q = &adap->sge.ethtxq[qidx + pi->first_qset];
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cpl = (struct cpl_tx_pkt_core *)pos;
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if (skb->ip_summed == CHECKSUM_PARTIAL)
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cntrl = TXPKT_L4CSUM_DIS_F | TXPKT_IPCSUM_DIS_F;
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ctrl0 = TXPKT_OPCODE_V(CPL_TX_PKT_XT) | TXPKT_INTF_V(pi->tx_chan) |
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TXPKT_PF_V(adap->pf);
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if (skb_vlan_tag_present(skb)) {
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q->vlan_ins++;
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cntrl |= TXPKT_VLAN_VLD_F | TXPKT_VLAN_V(skb_vlan_tag_get(skb));
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}
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cpl->ctrl0 = htonl(ctrl0);
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cpl->pack = htons(0);
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cpl->len = htons(skb->len);
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cpl->ctrl1 = cpu_to_be64(cntrl);
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pos += sizeof(struct cpl_tx_pkt_core);
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return pos;
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}
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inline void *copy_key_cpltx_pktxt(struct sk_buff *skb,
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struct net_device *dev,
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void *pos,
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struct ipsec_sa_entry *sa_entry)
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{
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struct adapter *adap;
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struct port_info *pi;
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struct sge_eth_txq *q;
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unsigned int len, qidx;
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struct _key_ctx *key_ctx;
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int left, eoq, key_len;
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pi = netdev_priv(dev);
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adap = pi->adapter;
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qidx = skb->queue_mapping;
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q = &adap->sge.ethtxq[qidx + pi->first_qset];
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len = sa_entry->enckey_len + sizeof(struct cpl_tx_pkt_core);
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key_len = sa_entry->kctx_len;
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/* end of queue, reset pos to start of queue */
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eoq = (void *)q->q.stat - pos;
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left = eoq;
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if (!eoq) {
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pos = q->q.desc;
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left = 64 * q->q.size;
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}
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/* Copy the Key context header */
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key_ctx = (struct _key_ctx *)pos;
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key_ctx->ctx_hdr = sa_entry->key_ctx_hdr;
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memcpy(key_ctx->salt, sa_entry->salt, MAX_SALT);
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pos += sizeof(struct _key_ctx);
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left -= sizeof(struct _key_ctx);
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if (likely(len <= left)) {
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memcpy(key_ctx->key, sa_entry->key, key_len);
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pos += key_len;
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} else {
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if (key_len <= left) {
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memcpy(pos, sa_entry->key, key_len);
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pos += key_len;
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} else {
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memcpy(pos, sa_entry->key, left);
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memcpy(q->q.desc, sa_entry->key + left,
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key_len - left);
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pos = q->q.desc + (key_len - left);
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}
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}
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/* Copy CPL TX PKT XT */
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pos = copy_cpltx_pktxt(skb, dev, pos);
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return pos;
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}
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inline void *chcr_crypto_wreq(struct sk_buff *skb,
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struct net_device *dev,
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void *pos,
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int credits,
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struct ipsec_sa_entry *sa_entry)
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{
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struct port_info *pi = netdev_priv(dev);
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struct adapter *adap = pi->adapter;
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unsigned int immdatalen = 0;
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unsigned int ivsize = GCM_ESP_IV_SIZE;
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struct chcr_ipsec_wr *wr;
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unsigned int flits;
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u32 wr_mid;
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int qidx = skb_get_queue_mapping(skb);
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struct sge_eth_txq *q = &adap->sge.ethtxq[qidx + pi->first_qset];
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unsigned int kctx_len = sa_entry->kctx_len;
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int qid = q->q.cntxt_id;
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atomic_inc(&adap->chcr_stats.ipsec_cnt);
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flits = calc_tx_sec_flits(skb, kctx_len);
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if (is_eth_imm(skb, kctx_len))
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immdatalen = skb->len;
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/* WR Header */
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wr = (struct chcr_ipsec_wr *)pos;
|
|
wr->wreq.op_to_compl = htonl(FW_WR_OP_V(FW_ULPTX_WR));
|
|
wr_mid = FW_CRYPTO_LOOKASIDE_WR_LEN16_V(DIV_ROUND_UP(flits, 2));
|
|
|
|
if (unlikely(credits < ETHTXQ_STOP_THRES)) {
|
|
netif_tx_stop_queue(q->txq);
|
|
q->q.stops++;
|
|
wr_mid |= FW_WR_EQUEQ_F | FW_WR_EQUIQ_F;
|
|
}
|
|
wr_mid |= FW_ULPTX_WR_DATA_F;
|
|
wr->wreq.flowid_len16 = htonl(wr_mid);
|
|
|
|
/* ULPTX */
|
|
wr->req.ulptx.cmd_dest = FILL_ULPTX_CMD_DEST(pi->port_id, qid);
|
|
wr->req.ulptx.len = htonl(DIV_ROUND_UP(flits, 2) - 1);
|
|
|
|
/* Sub-command */
|
|
wr->req.sc_imm.cmd_more = FILL_CMD_MORE(immdatalen);
|
|
wr->req.sc_imm.len = cpu_to_be32(sizeof(struct cpl_tx_sec_pdu) +
|
|
sizeof(wr->req.key_ctx) +
|
|
kctx_len +
|
|
sizeof(struct cpl_tx_pkt_core) +
|
|
immdatalen);
|
|
|
|
/* CPL_SEC_PDU */
|
|
wr->req.sec_cpl.op_ivinsrtofst = htonl(
|
|
CPL_TX_SEC_PDU_OPCODE_V(CPL_TX_SEC_PDU) |
|
|
CPL_TX_SEC_PDU_CPLLEN_V(2) |
|
|
CPL_TX_SEC_PDU_PLACEHOLDER_V(1) |
|
|
CPL_TX_SEC_PDU_IVINSRTOFST_V(
|
|
(skb_transport_offset(skb) +
|
|
sizeof(struct ip_esp_hdr) + 1)));
|
|
|
|
wr->req.sec_cpl.pldlen = htonl(skb->len);
|
|
|
|
wr->req.sec_cpl.aadstart_cipherstop_hi = FILL_SEC_CPL_CIPHERSTOP_HI(
|
|
(skb_transport_offset(skb) + 1),
|
|
(skb_transport_offset(skb) +
|
|
sizeof(struct ip_esp_hdr)),
|
|
(skb_transport_offset(skb) +
|
|
sizeof(struct ip_esp_hdr) +
|
|
GCM_ESP_IV_SIZE + 1), 0);
|
|
|
|
wr->req.sec_cpl.cipherstop_lo_authinsert =
|
|
FILL_SEC_CPL_AUTHINSERT(0, skb_transport_offset(skb) +
|
|
sizeof(struct ip_esp_hdr) +
|
|
GCM_ESP_IV_SIZE + 1,
|
|
sa_entry->authsize,
|
|
sa_entry->authsize);
|
|
wr->req.sec_cpl.seqno_numivs =
|
|
FILL_SEC_CPL_SCMD0_SEQNO(CHCR_ENCRYPT_OP, 1,
|
|
CHCR_SCMD_CIPHER_MODE_AES_GCM,
|
|
CHCR_SCMD_AUTH_MODE_GHASH,
|
|
sa_entry->hmac_ctrl,
|
|
ivsize >> 1);
|
|
wr->req.sec_cpl.ivgen_hdrlen = FILL_SEC_CPL_IVGEN_HDRLEN(0, 0, 1,
|
|
0, 0, 0);
|
|
|
|
pos += sizeof(struct fw_ulptx_wr) +
|
|
sizeof(struct ulp_txpkt) +
|
|
sizeof(struct ulptx_idata) +
|
|
sizeof(struct cpl_tx_sec_pdu);
|
|
|
|
pos = copy_key_cpltx_pktxt(skb, dev, pos, sa_entry);
|
|
|
|
return pos;
|
|
}
|
|
|
|
/**
|
|
* flits_to_desc - returns the num of Tx descriptors for the given flits
|
|
* @n: the number of flits
|
|
*
|
|
* Returns the number of Tx descriptors needed for the supplied number
|
|
* of flits.
|
|
*/
|
|
static inline unsigned int flits_to_desc(unsigned int n)
|
|
{
|
|
WARN_ON(n > SGE_MAX_WR_LEN / 8);
|
|
return DIV_ROUND_UP(n, 8);
|
|
}
|
|
|
|
static inline unsigned int txq_avail(const struct sge_txq *q)
|
|
{
|
|
return q->size - 1 - q->in_use;
|
|
}
|
|
|
|
static void eth_txq_stop(struct sge_eth_txq *q)
|
|
{
|
|
netif_tx_stop_queue(q->txq);
|
|
q->q.stops++;
|
|
}
|
|
|
|
static inline void txq_advance(struct sge_txq *q, unsigned int n)
|
|
{
|
|
q->in_use += n;
|
|
q->pidx += n;
|
|
if (q->pidx >= q->size)
|
|
q->pidx -= q->size;
|
|
}
|
|
|
|
/*
|
|
* chcr_ipsec_xmit called from ULD Tx handler
|
|
*/
|
|
int chcr_ipsec_xmit(struct sk_buff *skb, struct net_device *dev)
|
|
{
|
|
struct xfrm_state *x = xfrm_input_state(skb);
|
|
struct ipsec_sa_entry *sa_entry;
|
|
u64 *pos, *end, *before, cntrl, *sgl;
|
|
int qidx, left, credits;
|
|
unsigned int flits = 0, ndesc, kctx_len;
|
|
struct adapter *adap;
|
|
struct sge_eth_txq *q;
|
|
struct port_info *pi;
|
|
dma_addr_t addr[MAX_SKB_FRAGS + 1];
|
|
bool immediate = false;
|
|
|
|
if (!x->xso.offload_handle)
|
|
return NETDEV_TX_BUSY;
|
|
|
|
sa_entry = (struct ipsec_sa_entry *)x->xso.offload_handle;
|
|
kctx_len = sa_entry->kctx_len;
|
|
|
|
if (skb->sp->len != 1) {
|
|
out_free: dev_kfree_skb_any(skb);
|
|
return NETDEV_TX_OK;
|
|
}
|
|
|
|
pi = netdev_priv(dev);
|
|
adap = pi->adapter;
|
|
qidx = skb->queue_mapping;
|
|
q = &adap->sge.ethtxq[qidx + pi->first_qset];
|
|
|
|
cxgb4_reclaim_completed_tx(adap, &q->q, true);
|
|
cntrl = TXPKT_L4CSUM_DIS_F | TXPKT_IPCSUM_DIS_F;
|
|
|
|
flits = calc_tx_sec_flits(skb, sa_entry->kctx_len);
|
|
ndesc = flits_to_desc(flits);
|
|
credits = txq_avail(&q->q) - ndesc;
|
|
|
|
if (unlikely(credits < 0)) {
|
|
eth_txq_stop(q);
|
|
dev_err(adap->pdev_dev,
|
|
"%s: Tx ring %u full while queue awake! cred:%d %d %d flits:%d\n",
|
|
dev->name, qidx, credits, ndesc, txq_avail(&q->q),
|
|
flits);
|
|
return NETDEV_TX_BUSY;
|
|
}
|
|
|
|
if (is_eth_imm(skb, kctx_len))
|
|
immediate = true;
|
|
|
|
if (!immediate &&
|
|
unlikely(cxgb4_map_skb(adap->pdev_dev, skb, addr) < 0)) {
|
|
q->mapping_err++;
|
|
goto out_free;
|
|
}
|
|
|
|
pos = (u64 *)&q->q.desc[q->q.pidx];
|
|
before = (u64 *)pos;
|
|
end = (u64 *)pos + flits;
|
|
/* Setup IPSec CPL */
|
|
pos = (void *)chcr_crypto_wreq(skb, dev, (void *)pos,
|
|
credits, sa_entry);
|
|
if (before > (u64 *)pos) {
|
|
left = (u8 *)end - (u8 *)q->q.stat;
|
|
end = (void *)q->q.desc + left;
|
|
}
|
|
if (pos == (u64 *)q->q.stat) {
|
|
left = (u8 *)end - (u8 *)q->q.stat;
|
|
end = (void *)q->q.desc + left;
|
|
pos = (void *)q->q.desc;
|
|
}
|
|
|
|
sgl = (void *)pos;
|
|
if (immediate) {
|
|
cxgb4_inline_tx_skb(skb, &q->q, sgl);
|
|
dev_consume_skb_any(skb);
|
|
} else {
|
|
int last_desc;
|
|
|
|
cxgb4_write_sgl(skb, &q->q, (void *)sgl, end,
|
|
0, addr);
|
|
skb_orphan(skb);
|
|
|
|
last_desc = q->q.pidx + ndesc - 1;
|
|
if (last_desc >= q->q.size)
|
|
last_desc -= q->q.size;
|
|
q->q.sdesc[last_desc].skb = skb;
|
|
q->q.sdesc[last_desc].sgl = (struct ulptx_sgl *)sgl;
|
|
}
|
|
txq_advance(&q->q, ndesc);
|
|
|
|
cxgb4_ring_tx_db(adap, &q->q, ndesc);
|
|
return NETDEV_TX_OK;
|
|
}
|