linux/drivers/dma/dw
Serge Semin 6d9459d040 dmaengine: dw: Activate FIFO-mode for memory peripherals only
CFGx.FIFO_MODE field controls a DMA-controller "FIFO readiness" criterion.
In other words it determines when to start pushing data out of a DW
DMAC channel FIFO to a destination peripheral or from a source
peripheral to the DW DMAC channel FIFO. Currently FIFO-mode is set to one
for all DW DMAC channels. It means they are tuned to flush data out of
FIFO (to a memory peripheral or by accepting the burst transaction
requests) when FIFO is at least half-full (except at the end of the block
transfer, when FIFO-flush mode is activated) and are configured to get
data to the FIFO when it's at least half-empty.

Such configuration is a good choice when there is no slave device involved
in the DMA transfers. In that case the number of bursts per block is less
than when CFGx.FIFO_MODE = 0 and, hence, the bus utilization will improve.
But the latency of DMA transfers may increase when CFGx.FIFO_MODE = 1,
since DW DMAC will wait for the channel FIFO contents to be either
half-full or half-empty depending on having the destination or the source
transfers. Such latencies might be dangerous in case if the DMA transfers
are expected to be performed from/to a slave device. Since normally
peripheral devices keep data in internal FIFOs, any latency at some
critical moment may cause one being overflown and consequently losing
data. This especially concerns a case when either a peripheral device is
relatively fast or the DW DMAC engine is relatively slow with respect to
the incoming data pace.

In order to solve problems, which might be caused by the latencies
described above, let's enable the FIFO half-full/half-empty "FIFO
readiness" criterion only for DMA transfers with no slave device involved.
Thanks to the commit 99ba8b9b0d ("dmaengine: dw: Initialize channel
before each transfer") we can freely do that in the generic
dw_dma_initialize_chan() method.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20200731200826.9292-3-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-08-17 11:58:31 +05:30
..
acpi.c dmaengine: dw: Register ACPI DMA controller for PCI that has companion 2020-06-16 21:54:47 +05:30
core.c Merge branch 'for-linus' into fixes 2020-08-05 19:02:07 +05:30
dw.c dmaengine: dw: Activate FIFO-mode for memory peripherals only 2020-08-17 11:58:31 +05:30
idma32.c dmaengine: dw: Don't pollute CTL_LO on iDMA 32-bit 2019-01-07 17:57:13 +05:30
internal.h dmaengine: dw: platform: Split OF helpers to separate module 2019-08-21 09:41:28 +05:30
Kconfig dmaengine: dw: convert to SPDX identifiers 2019-01-07 17:57:13 +05:30
Makefile dmaengine: dw: Replace 'objs' by 'y' 2020-06-16 21:54:47 +05:30
of.c dmaengine: dw: Introduce max burst length hw config 2020-07-27 14:30:55 +05:30
pci.c dmaengine: dw: Register ACPI DMA controller for PCI that has companion 2020-06-16 21:54:47 +05:30
platform.c dmaengine: dw: platform: Mark 'hclk' clock optional 2019-10-14 13:51:44 +05:30
regs.h dmaengine: dw: Introduce max burst length hw config 2020-07-27 14:30:55 +05:30