forked from Minki/linux
6c9da387c8
The CRG(Clock and Reset Generator) block provides clock and reset signals for other modules in hi3519 soc. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
132 lines
4.0 KiB
C
132 lines
4.0 KiB
C
/*
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* Hi3519 Clock Driver
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*
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* Copyright (c) 2015-2016 HiSilicon Technologies Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <dt-bindings/clock/hi3519-clock.h>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include "clk.h"
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#include "reset.h"
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#define HI3519_INNER_CLK_OFFSET 64
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#define HI3519_FIXED_24M 65
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#define HI3519_FIXED_50M 66
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#define HI3519_FIXED_75M 67
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#define HI3519_FIXED_125M 68
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#define HI3519_FIXED_150M 69
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#define HI3519_FIXED_200M 70
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#define HI3519_FIXED_250M 71
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#define HI3519_FIXED_300M 72
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#define HI3519_FIXED_400M 73
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#define HI3519_FMC_MUX 74
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#define HI3519_NR_CLKS 128
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static const struct hisi_fixed_rate_clock hi3519_fixed_rate_clks[] = {
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{ HI3519_FIXED_24M, "24m", NULL, 0, 24000000, },
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{ HI3519_FIXED_50M, "50m", NULL, 0, 50000000, },
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{ HI3519_FIXED_75M, "75m", NULL, 0, 75000000, },
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{ HI3519_FIXED_125M, "125m", NULL, 0, 125000000, },
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{ HI3519_FIXED_150M, "150m", NULL, 0, 150000000, },
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{ HI3519_FIXED_200M, "200m", NULL, 0, 200000000, },
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{ HI3519_FIXED_250M, "250m", NULL, 0, 250000000, },
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{ HI3519_FIXED_300M, "300m", NULL, 0, 300000000, },
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{ HI3519_FIXED_400M, "400m", NULL, 0, 400000000, },
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};
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static const char *const fmc_mux_p[] = {
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"24m", "75m", "125m", "150m", "200m", "250m", "300m", "400m", };
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static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
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static const struct hisi_mux_clock hi3519_mux_clks[] = {
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{ HI3519_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
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CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, },
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};
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static const struct hisi_gate_clock hi3519_gate_clks[] = {
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{ HI3519_FMC_CLK, "clk_fmc", "fmc_mux",
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CLK_SET_RATE_PARENT, 0xc0, 1, 0, },
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{ HI3519_UART0_CLK, "clk_uart0", "24m",
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CLK_SET_RATE_PARENT, 0xe4, 20, 0, },
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{ HI3519_UART1_CLK, "clk_uart1", "24m",
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CLK_SET_RATE_PARENT, 0xe4, 21, 0, },
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{ HI3519_UART2_CLK, "clk_uart2", "24m",
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CLK_SET_RATE_PARENT, 0xe4, 22, 0, },
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{ HI3519_UART3_CLK, "clk_uart3", "24m",
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CLK_SET_RATE_PARENT, 0xe4, 23, 0, },
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{ HI3519_UART4_CLK, "clk_uart4", "24m",
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CLK_SET_RATE_PARENT, 0xe4, 24, 0, },
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{ HI3519_SPI0_CLK, "clk_spi0", "50m",
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CLK_SET_RATE_PARENT, 0xe4, 16, 0, },
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{ HI3519_SPI1_CLK, "clk_spi1", "50m",
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CLK_SET_RATE_PARENT, 0xe4, 17, 0, },
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{ HI3519_SPI2_CLK, "clk_spi2", "50m",
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CLK_SET_RATE_PARENT, 0xe4, 18, 0, },
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};
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static int hi3519_clk_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct hisi_clock_data *clk_data;
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struct hisi_reset_controller *rstc;
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rstc = hisi_reset_init(np);
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if (!rstc)
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return -ENOMEM;
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clk_data = hisi_clk_init(np, HI3519_NR_CLKS);
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if (!clk_data) {
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hisi_reset_exit(rstc);
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return -ENODEV;
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}
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hisi_clk_register_fixed_rate(hi3519_fixed_rate_clks,
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ARRAY_SIZE(hi3519_fixed_rate_clks),
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clk_data);
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hisi_clk_register_mux(hi3519_mux_clks, ARRAY_SIZE(hi3519_mux_clks),
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clk_data);
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hisi_clk_register_gate(hi3519_gate_clks,
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ARRAY_SIZE(hi3519_gate_clks), clk_data);
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return 0;
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}
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static const struct of_device_id hi3519_clk_match_table[] = {
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{ .compatible = "hisilicon,hi3519-crg" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, hi3519_clk_match_table);
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static struct platform_driver hi3519_clk_driver = {
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.probe = hi3519_clk_probe,
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.driver = {
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.name = "hi3519-clk",
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.of_match_table = hi3519_clk_match_table,
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},
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};
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static int __init hi3519_clk_init(void)
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{
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return platform_driver_register(&hi3519_clk_driver);
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}
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core_initcall(hi3519_clk_init);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("HiSilicon Hi3519 Clock Driver");
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