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6c2be5cf1d
linux/arch/mips/alchemy
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Manuel Lauss 6c2be5cf1d MIPS: Alchemy: handle db1200 cpld ints as they come in 
Remove the loop in the cascade handler and instead unconditionally
handle just the first set interrupt coming from the CPLD.

This gets rid of a lot of spurious interrupts being triggered for
the SMSC91111 ethernet chip especially under high(er) IDE load:
"eth0: spurious interrupt (mask = 0xb3)"

Verified on DB1200 and DB1300.

Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3288/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-07-23 13:53:38 +01:00
..
common MIPS: Alchemy: Increase minimum timeout for 32kHz timer. 2012-02-20 18:33:18 +01:00
devboards MIPS: Alchemy: handle db1200 cpld ints as they come in 2012-07-23 13:53:38 +01:00
board-gpr.c MIPS: Alchemy: merge GPR/MTX-1/XXS1500 board code into single files 2011-12-07 22:02:06 +00:00
board-mtx1.c MIPS: Alchemy: merge GPR/MTX-1/XXS1500 board code into single files 2011-12-07 22:02:06 +00:00
board-xxs1500.c MIPS: Alchemy: merge GPR/MTX-1/XXS1500 board code into single files 2011-12-07 22:02:06 +00:00
Kconfig MIPS: Alchemy: one kernel for DB1000/DB1500/DB1100 2011-12-07 22:02:07 +00:00
Makefile MIPS: Alchemy: merge GPR/MTX-1/XXS1500 board code into single files 2011-12-07 22:02:06 +00:00
Platform MIPS: Alchemy: remove unused board headers 2011-12-08 10:42:15 +00:00