05454c26eb
Following files contains code that is common to all intel mid soc's. So renamed them as below. mrst/mrst.c -> intel-mid/intel-mid.c mrst/vrtc.c -> intel-mid/intel_mid_vrtc.c mrst/early_printk_mrst.c -> intel-mid/intel_mid_vrtc.c pci/mrst.c -> pci/intel_mid_pci.c Also, renamed the corresponding header files and made changes to the driver files that included these header files. To ensure that there are no functional changes, I have compared the objdump of renamed files before and after rename and found that the only difference is file name change. Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Link: http://lkml.kernel.org/r/1382049336-21316-4-git-send-email-david.a.cohen@linux.intel.com Signed-off-by: David Cohen <david.a.cohen@linux.intel.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
82 lines
2.0 KiB
C
82 lines
2.0 KiB
C
/*
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* intel-mid.h: Intel MID specific setup code
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*
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* (C) Copyright 2009 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*/
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#ifndef _ASM_X86_INTEL_MID_H
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#define _ASM_X86_INTEL_MID_H
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#include <linux/sfi.h>
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extern int pci_mrst_init(void);
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extern int __init sfi_parse_mrtc(struct sfi_table_header *table);
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extern int sfi_mrtc_num;
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extern struct sfi_rtc_table_entry sfi_mrtc_array[];
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/*
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* Medfield is the follow-up of Moorestown, it combines two chip solution into
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* one. Other than that it also added always-on and constant tsc and lapic
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* timers. Medfield is the platform name, and the chip name is called Penwell
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* we treat Medfield/Penwell as a variant of Moorestown. Penwell can be
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* identified via MSRs.
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*/
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enum mrst_cpu_type {
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/* 1 was Moorestown */
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MRST_CPU_CHIP_PENWELL = 2,
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};
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extern enum mrst_cpu_type __mrst_cpu_chip;
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#ifdef CONFIG_X86_INTEL_MID
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static inline enum mrst_cpu_type mrst_identify_cpu(void)
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{
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return __mrst_cpu_chip;
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}
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#else /* !CONFIG_X86_INTEL_MID */
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#define mrst_identify_cpu() (0)
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#endif /* !CONFIG_X86_INTEL_MID */
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enum mrst_timer_options {
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MRST_TIMER_DEFAULT,
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MRST_TIMER_APBT_ONLY,
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MRST_TIMER_LAPIC_APBT,
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};
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extern enum mrst_timer_options mrst_timer_options;
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/*
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* Penwell uses spread spectrum clock, so the freq number is not exactly
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* the same as reported by MSR based on SDM.
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*/
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#define PENWELL_FSB_FREQ_83SKU 83200
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#define PENWELL_FSB_FREQ_100SKU 99840
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#define SFI_MTMR_MAX_NUM 8
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#define SFI_MRTC_MAX 8
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extern struct console early_mrst_console;
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extern void mrst_early_console_init(void);
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extern struct console early_hsu_console;
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extern void hsu_early_console_init(const char *);
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extern void intel_scu_devices_create(void);
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extern void intel_scu_devices_destroy(void);
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/* VRTC timer */
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#define MRST_VRTC_MAP_SZ (1024)
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/*#define MRST_VRTC_PGOFFSET (0xc00) */
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extern void mrst_rtc_init(void);
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#endif /* _ASM_X86_INTEL_MID_H */
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