Nicholas Kazlauskas 6c0984d53b drm/amd/display: Raise dispclk value for dce_update_clocks ... [Why] The DISPCLK value was previously requested to be 15% higher for all ASICS that went through the dce110 bandwidth code path. As part of a refactoring of dce_clocks and dce110 set_bandwidth this was removed for power saving considerations. This changed caused corruption under certain display configurations. Originally thought to be Vega specific, it was also observed on Polaris. [How] The 15% is brought back but its placement differs from the original patch. This boost should only be enable while DFS bypass is inactive. This (like the Vega patch) is also a workaround that should be removed after the root cause is identified. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2018-10-09 17:04:13 -05:00
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amdgpu_dm	drm/amd/display: Flatten irq handler data struct	2018-10-09 17:03:38 -05:00
dc	drm/amd/display: Raise dispclk value for dce_update_clocks	2018-10-09 17:04:13 -05:00
include	drm/amd/display: Add a check-function for virtual signal type	2018-10-09 17:01:48 -05:00
modules	drm/amd/display: remove redundant null pointer check before kfree	2018-09-26 21:09:12 -05:00
Kconfig	drm/amd/display: Add DC config flag for Raven2 (v2)	2018-09-14 09:36:56 -05:00
Makefile	drm/amd/display: Enable Stereo in Dal3	2018-08-27 11:10:57 -05:00
TODO	drm/amd/display: Convert remaining loggers off dc_logger	2018-07-13 14:48:42 -05:00