Jerome Brunet 6b71aceceb clk: meson: axg: add the fractional part of the fixed_pll ... The fixed_pll also has a fractional part. On axg s400 board, without this parameter, the calculated rate is off by ~8Mhz (0,4%). The fixed_pll being the root of the peripheral clock tree, this error is propagated to the rest of the clocks Adding the definition of the parameter fixes the problem Fixes: 78b4af312f ("clk: meson-axg: add clock controller drivers") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>		2018-02-12 09:49:23 +01:00
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axg.c	clk: meson: axg: add the fractional part of the fixed_pll	2018-02-12 09:49:23 +01:00
axg.h	clk: meson-axg: add clock controller drivers	2017-12-14 10:19:37 +01:00
clk-audio-divider.c	clk: meson: add audio clock divider support	2017-04-07 16:50:44 +02:00
clk-cpu.c	clk: meson8b: clean up cpu clocks	2016-06-22 18:02:35 -07:00
clk-mpll.c	clk: meson: mpll: use 64-bit maths in params_from_rate	2017-12-23 23:14:20 +01:00
clk-pll.c	clk: meson: fix rate calculation of plls with a fractional part	2018-02-12 09:49:23 +01:00
clkc.h	clk: meson: add od3 to the pll driver	2018-02-12 09:49:23 +01:00
gxbb-aoclk-32k.c	clk: meson: gxbb-aoclk: Add CEC 32k clock	2017-08-04 18:02:02 +02:00
gxbb-aoclk-regmap.c	clk: meson: gxbb-aoclk: Switch to regmap for register access	2017-08-04 18:02:01 +02:00
gxbb-aoclk.c	clk: meson: gxbb-aoclk: Add CEC 32k clock	2017-08-04 18:02:02 +02:00
gxbb-aoclk.h	clk: meson: gxbb-aoclk: Add CEC 32k clock	2017-08-04 18:02:02 +02:00
gxbb.c	clk: meson: gxbb: add the fractional part of the fixed_pll	2018-02-12 09:49:23 +01:00
gxbb.h	clk: meson: fix rate calculation of plls with a fractional part	2018-02-12 09:49:23 +01:00
Kconfig	clk: meson-axg: add clock controller drivers	2017-12-14 10:19:37 +01:00
Makefile	clk: meson-axg: add clock controller drivers	2017-12-14 10:19:37 +01:00
meson8b.c	clk: meson: make the spinlock naming more specific	2017-12-14 10:12:41 +01:00
meson8b.h	clk: meson: meson8b: register the built-in reset controller	2017-08-04 18:01:58 +02:00