forked from Minki/linux
5e9972cd6f
The driver currently does not take into account the minimum sample time as per the Figure 6-8 Chapter 9.1.1 12-bit ADC electrical characteristics. We set a static amount of cycles instead of considering the sample time as a given value, which depends on hardware characteristics. Determine sampling frequencies by first reading the device tree property node and then calculating the required Long Sample Time Adder (LSTAdder) value, based on the ADC clock frequency and sample time value obtained from the device tree. This LSTAdder value is then used for calculating the sampling frequencies possible. In case the sample time property is not specified through the device tree, a safe default value of 1000ns is assumed. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Acked-by: Stefan Agner <stefan@agner.ch> Acked-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
37 lines
1.5 KiB
Plaintext
37 lines
1.5 KiB
Plaintext
Freescale vf610 Analog to Digital Converter bindings
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The devicetree bindings are for the new ADC driver written for
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vf610/i.MX6slx and upward SoCs from Freescale.
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Required properties:
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- compatible: Should contain "fsl,vf610-adc"
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- reg: Offset and length of the register set for the device
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- interrupts: Should contain the interrupt for the device
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- clocks: The clock is needed by the ADC controller, ADC clock source is ipg clock.
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- clock-names: Must contain "adc", matching entry in the clocks property.
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- vref-supply: The regulator supply ADC reference voltage.
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Recommended properties:
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- fsl,adck-max-frequency: Maximum frequencies according to datasheets operating
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requirements. Three values are required, depending on conversion mode:
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- Frequency in normal mode (ADLPC=0, ADHSC=0)
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- Frequency in high-speed mode (ADLPC=0, ADHSC=1)
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- Frequency in low-power mode (ADLPC=1, ADHSC=0)
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- min-sample-time: Minimum sampling time in nanoseconds. This value has
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to be chosen according to the conversion mode and the connected analog
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source resistance (R_as) and capacitance (C_as). Refer the datasheet's
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operating requirements. A safe default across a wide range of R_as and
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C_as as well as conversion modes is 1000ns.
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Example:
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adc0: adc@4003b000 {
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compatible = "fsl,vf610-adc";
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reg = <0x4003b000 0x1000>;
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interrupts = <0 53 0x04>;
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clocks = <&clks VF610_CLK_ADC0>;
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clock-names = "adc";
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fsl,adck-max-frequency = <30000000>, <40000000>,
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<20000000>;
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vref-supply = <®_vcc_3v3_mcu>;
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};
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