forked from Minki/linux
d0e286415d
A mbigen hardware module can contain more than one device node. These device
nodes contain the same register definition.
mbigen_dev1:intc_dev1 {
...
reg = <0x0 0xc0080000 0x0 0x10000>;
...
};
mbigen_dev2:intc_dev2 {
...
reg = <0x0 0xc0080000 0x0 0x10000>;
...
};
In this case both devices try to request the same resource resulting in a
resource conflict.
To address this problem the devices need to be subnodes of the mbigen hardware
module, which then contains the unique register space.
[ tglx: Massaged changelog ]
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Ma Jun <majun258@huawei.com>
Cc: jason@lakedaemon.net
Cc: marc.zyngier@arm.com
Cc: Catalin.Marinas@arm.com
Cc: guohanjun@huawei.com
Cc: Will.Deacon@arm.com
Cc: huxinwei@huawei.com
Cc: lizefan@huawei.com
Cc: dingtianhong@huawei.com
Cc: zhaojunhua@hisilicon.com
Cc: liguozhu@hisilicon.com
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/20160203111602.GA1234@leverpostej
Link: http://lkml.kernel.org/r/1458203641-17172-2-git-send-email-majun258@huawei.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
87 lines
2.5 KiB
Plaintext
87 lines
2.5 KiB
Plaintext
Hisilicon mbigen device tree bindings.
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=======================================
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Mbigen means: message based interrupt generator.
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MBI is kind of msi interrupt only used on Non-PCI devices.
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To reduce the wired interrupt number connected to GIC,
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Hisilicon designed mbigen to collect and generate interrupt.
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Non-pci devices can connect to mbigen and generate the
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interrupt by writing ITS register.
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The mbigen chip and devices connect to mbigen have the following properties:
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Mbigen main node required properties:
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-------------------------------------------
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- compatible: Should be "hisilicon,mbigen-v2"
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- reg: Specifies the base physical address and size of the Mbigen
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registers.
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Mbigen sub node required properties:
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------------------------------------------
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- interrupt controller: Identifies the node as an interrupt controller
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- msi-parent: Specifies the MSI controller this mbigen use.
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For more detail information,please refer to the generic msi-parent binding in
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Documentation/devicetree/bindings/interrupt-controller/msi.txt.
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- num-pins: the total number of pins implemented in this Mbigen
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instance.
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- #interrupt-cells : Specifies the number of cells needed to encode an
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interrupt source. The value must be 2.
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The 1st cell is hardware pin number of the interrupt.This number is local to
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each mbigen chip and in the range from 0 to the maximum interrupts number
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of the mbigen.
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The 2nd cell is the interrupt trigger type.
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The value of this cell should be:
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1: rising edge triggered
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or
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4: high level triggered
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Examples:
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mbigen_chip_dsa {
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compatible = "hisilicon,mbigen-v2";
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reg = <0x0 0xc0080000 0x0 0x10000>;
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mbigen_gmac:intc_gmac {
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interrupt-controller;
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msi-parent = <&its_dsa 0x40b1c>;
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num-pins = <9>;
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#interrupt-cells = <2>;
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};
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mbigen_i2c:intc_i2c {
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interrupt-controller;
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msi-parent = <&its_dsa 0x40b0e>;
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num-pins = <2>;
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#interrupt-cells = <2>;
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};
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};
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Devices connect to mbigen required properties:
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----------------------------------------------------
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-interrupt-parent: Specifies the mbigen device node which device connected.
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-interrupts:Specifies the interrupt source.
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For the specific information of each cell in this property,please refer to
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the "interrupt-cells" description mentioned above.
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Examples:
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gmac0: ethernet@c2080000 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0xc2080000 0 0x20000>,
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<0 0xc0000000 0 0x1000>;
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interrupt-parent = <&mbigen_device_gmac>;
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interrupts = <656 1>,
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<657 1>;
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};
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