forked from Minki/linux
40aad3c1a9
The device_type property is deprecated for the flattened device tree and the value "ethernet-phy" has never been defined as having a useful meaning. Neither the kernel nor u-boot depend on it. It should never have appeared in PHY bindings. This patch removes all references to "ethernet-phy" as a device_type value from the documentation and the .dts files. This patch was generated mechanically with the following command and then verified by looking at the diff. sed -i '/"ethernet-phy"/d' `git grep -l '"ethernet-phy"'` Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
294 lines
7.0 KiB
Plaintext
294 lines
7.0 KiB
Plaintext
/*
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* SBC8548 Device Tree Source
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*
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* Copyright 2007 Wind River Systems Inc.
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*
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* Paul Gortmaker (see MAINTAINERS for contact information)
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/{
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soc8548@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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ranges = <0x00000000 0xe0000000 0x00100000>;
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bus-frequency = <0>;
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compatible = "simple-bus";
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ecm-law@0 {
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compatible = "fsl,ecm-law";
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reg = <0x0 0x1000>;
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fsl,num-laws = <10>;
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};
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ecm@1000 {
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compatible = "fsl,mpc8548-ecm", "fsl,ecm";
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reg = <0x1000 0x1000>;
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interrupts = <17 2>;
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interrupt-parent = <&mpic>;
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};
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memory-controller@2000 {
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compatible = "fsl,mpc8548-memory-controller";
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reg = <0x2000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <0x12 0x2>;
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};
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L2: l2-cache-controller@20000 {
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compatible = "fsl,mpc8548-l2-cache-controller";
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reg = <0x20000 0x1000>;
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cache-line-size = <0x20>; // 32 bytes
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cache-size = <0x80000>; // L2, 512K
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interrupt-parent = <&mpic>;
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interrupts = <0x10 0x2>;
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};
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <0x2b 0x2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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i2c@3100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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compatible = "fsl-i2c";
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reg = <0x3100 0x100>;
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interrupts = <0x2b 0x2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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dma@21300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
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reg = <0x21300 0x4>;
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ranges = <0x0 0x21100 0x200>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8548-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <20 2>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8548-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&mpic>;
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interrupts = <21 2>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8548-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&mpic>;
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interrupts = <22 2>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8548-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupt-parent = <&mpic>;
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interrupts = <23 2>;
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};
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};
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enet0: ethernet@24000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <0>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x24000 0x1000>;
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ranges = <0x0 0x24000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
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interrupt-parent = <&mpic>;
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tbi-handle = <&tbi0>;
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phy-handle = <&phy0>;
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-mdio";
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reg = <0x520 0x20>;
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phy0: ethernet-phy@19 {
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interrupt-parent = <&mpic>;
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interrupts = <0x6 0x1>;
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reg = <0x19>;
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};
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phy1: ethernet-phy@1a {
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interrupt-parent = <&mpic>;
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interrupts = <0x7 0x1>;
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reg = <0x1a>;
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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enet1: ethernet@25000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <1>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x25000 0x1000>;
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ranges = <0x0 0x25000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
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interrupt-parent = <&mpic>;
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tbi-handle = <&tbi1>;
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phy-handle = <&phy1>;
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-tbi";
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reg = <0x520 0x20>;
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tbi1: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "fsl,ns16550", "ns16550";
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reg = <0x4500 0x100>; // reg base, size
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clock-frequency = <0>; // should we fill in in uboot?
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interrupts = <0x2a 0x2>;
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interrupt-parent = <&mpic>;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "fsl,ns16550", "ns16550";
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reg = <0x4600 0x100>; // reg base, size
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clock-frequency = <0>; // should we fill in in uboot?
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interrupts = <0x2a 0x2>;
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interrupt-parent = <&mpic>;
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};
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global-utilities@e0000 { //global utilities reg
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compatible = "fsl,mpc8548-guts";
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reg = <0xe0000 0x1000>;
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fsl,has-rstcr;
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};
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crypto@30000 {
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compatible = "fsl,sec2.1", "fsl,sec2.0";
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reg = <0x30000 0x10000>;
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interrupts = <45 2>;
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interrupt-parent = <&mpic>;
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fsl,num-channels = <4>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0xfe>;
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fsl,descriptor-types-mask = <0x12b0ebf>;
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};
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mpic: pic@40000 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x40000 0x40000>;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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};
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};
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pci0: pci@e0008000 {
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x01 (PCI-X slot) @66MHz */
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0x0800 0x0 0x0 0x1 &mpic 0x2 0x1
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0x0800 0x0 0x0 0x2 &mpic 0x3 0x1
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0x0800 0x0 0x0 0x3 &mpic 0x4 0x1
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0x0800 0x0 0x0 0x4 &mpic 0x1 0x1
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/* IDSEL 0x11 (PCI, 3.3V 32bit) @33MHz */
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0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
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0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
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0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
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0x8800 0x0 0x0 0x4 &mpic 0x1 0x1>;
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interrupt-parent = <&mpic>;
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interrupts = <0x18 0x2>;
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bus-range = <0 0>;
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ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
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0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00800000>;
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clock-frequency = <66000000>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xe0008000 0x1000>;
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compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
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device_type = "pci";
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};
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pci1: pcie@e000a000 {
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x0 (PEX) */
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0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
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0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
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0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
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0x0000 0x0 0x0 0x4 &mpic 0x3 0x1>;
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interrupt-parent = <&mpic>;
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interrupts = <0x1a 0x2>;
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bus-range = <0x0 0xff>;
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ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
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0x01000000 0x0 0x00000000 0xe2800000 0x0 0x08000000>;
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clock-frequency = <33000000>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xe000a000 0x1000>;
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compatible = "fsl,mpc8548-pcie";
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device_type = "pci";
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pcie@0 {
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reg = <0x0 0x0 0x0 0x0 0x0>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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ranges = <0x02000000 0x0 0xa0000000
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0x02000000 0x0 0xa0000000
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0x0 0x10000000
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0x01000000 0x0 0x00000000
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0x01000000 0x0 0x00000000
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0x0 0x00800000>;
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};
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};
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};
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