659fb32d1b
This fixes a regression introduced by e59347a "arm: orion:
Use generic irq chip".
Depending on the device, interrupts acknowledgement is done by setting
or by clearing a dedicated register. Replace irq_gc_ack() with some
{set,clr}_bit variants allows to handle both cases.
Note that this patch affects the following SoCs: Davinci, Samsung and
Orion. Except for this last, the change is minor: irq_gc_ack() is just
renamed into irq_gc_ack_set_bit().
For the Orion SoCs, the edge GPIO interrupts support is currently
broken. irq_gc_ack() try to acknowledge a such interrupt by setting
the corresponding cause register bit. The Orion GPIO device expect the
opposite. To fix this issue, the irq_gc_ack_clr_bit() variant is used.
Tested on Network Space v2.
Reported-by: Joey Oravec <joravec@drewtech.com>
Signed-off-by: Simon Guinot <sguinot@lacie.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
112 lines
3.5 KiB
C
112 lines
3.5 KiB
C
/*
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* Interrupt handler for DaVinci boards.
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*
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* Copyright (C) 2006 Texas Instruments.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/cputype.h>
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#include <mach/common.h>
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#include <asm/mach/irq.h>
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#define FIQ_REG0_OFFSET 0x0000
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#define FIQ_REG1_OFFSET 0x0004
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#define IRQ_REG0_OFFSET 0x0008
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#define IRQ_REG1_OFFSET 0x000C
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#define IRQ_ENT_REG0_OFFSET 0x0018
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#define IRQ_ENT_REG1_OFFSET 0x001C
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#define IRQ_INCTL_REG_OFFSET 0x0020
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#define IRQ_EABASE_REG_OFFSET 0x0024
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#define IRQ_INTPRI0_REG_OFFSET 0x0030
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#define IRQ_INTPRI7_REG_OFFSET 0x004C
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static inline void davinci_irq_writel(unsigned long value, int offset)
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{
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__raw_writel(value, davinci_intc_base + offset);
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}
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static __init void
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davinci_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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gc = irq_alloc_generic_chip("AINTC", 1, irq_start, base, handle_edge_irq);
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ct = gc->chip_types;
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ct->chip.irq_ack = irq_gc_ack_set_bit;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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ct->regs.ack = IRQ_REG0_OFFSET;
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ct->regs.mask = IRQ_ENT_REG0_OFFSET;
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irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
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IRQ_NOREQUEST | IRQ_NOPROBE, 0);
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}
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/* ARM Interrupt Controller Initialization */
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void __init davinci_irq_init(void)
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{
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unsigned i, j;
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const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios;
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davinci_intc_type = DAVINCI_INTC_TYPE_AINTC;
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davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_4K);
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if (WARN_ON(!davinci_intc_base))
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return;
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/* Clear all interrupt requests */
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davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
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davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
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davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
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davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
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/* Disable all interrupts */
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davinci_irq_writel(0x0, IRQ_ENT_REG0_OFFSET);
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davinci_irq_writel(0x0, IRQ_ENT_REG1_OFFSET);
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/* Interrupts disabled immediately, IRQ entry reflects all */
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davinci_irq_writel(0x0, IRQ_INCTL_REG_OFFSET);
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/* we don't use the hardware vector table, just its entry addresses */
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davinci_irq_writel(0, IRQ_EABASE_REG_OFFSET);
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/* Clear all interrupt requests */
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davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
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davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
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davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
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davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
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for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) {
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u32 pri;
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for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++)
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pri |= (*davinci_def_priorities & 0x07) << j;
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davinci_irq_writel(pri, i);
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}
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for (i = 0, j = 0; i < davinci_soc_info.intc_irq_num; i += 32, j += 0x04)
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davinci_alloc_gc(davinci_intc_base + j, i, 32);
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irq_set_handler(IRQ_TINT1_TINT34, handle_level_irq);
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}
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