forked from Minki/linux
6a0bfbbe20
The Microsemi PHYs have multiple banks of registers (called pages). Registers can only be accessed from one page, if we need a register from another page, we need to switch the page and the registers of all other pages are not accessible anymore. Basically, to read register 5 from page 0, 1, 2, etc., you do the same phy_read(phydev, 5); but you need to set the desired page beforehand. In order to guarantee that two concurrent functions do not change the page, we need to do some locking per page. This can be achieved with the use of phy_select_page and phy_restore_page functions but phy_write/read calls in-between those two functions shall be replaced by their lock-free alternative __phy_write/read. Let's migrate this driver to those functions. Suggested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
762 lines
20 KiB
C
762 lines
20 KiB
C
/*
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* Driver for Microsemi VSC85xx PHYs
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*
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* Author: Nagaraju Lakkaraju
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* License: Dual MIT/GPL
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* Copyright (c) 2016 Microsemi Corporation
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mdio.h>
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#include <linux/mii.h>
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#include <linux/phy.h>
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#include <linux/of.h>
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#include <linux/netdevice.h>
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#include <dt-bindings/net/mscc-phy-vsc8531.h>
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enum rgmii_rx_clock_delay {
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RGMII_RX_CLK_DELAY_0_2_NS = 0,
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RGMII_RX_CLK_DELAY_0_8_NS = 1,
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RGMII_RX_CLK_DELAY_1_1_NS = 2,
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RGMII_RX_CLK_DELAY_1_7_NS = 3,
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RGMII_RX_CLK_DELAY_2_0_NS = 4,
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RGMII_RX_CLK_DELAY_2_3_NS = 5,
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RGMII_RX_CLK_DELAY_2_6_NS = 6,
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RGMII_RX_CLK_DELAY_3_4_NS = 7
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};
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/* Microsemi VSC85xx PHY registers */
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/* IEEE 802. Std Registers */
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#define MSCC_PHY_BYPASS_CONTROL 18
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#define DISABLE_HP_AUTO_MDIX_MASK 0x0080
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#define DISABLE_PAIR_SWAP_CORR_MASK 0x0020
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#define DISABLE_POLARITY_CORR_MASK 0x0010
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#define MSCC_PHY_EXT_PHY_CNTL_1 23
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#define MAC_IF_SELECTION_MASK 0x1800
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#define MAC_IF_SELECTION_GMII 0
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#define MAC_IF_SELECTION_RMII 1
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#define MAC_IF_SELECTION_RGMII 2
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#define MAC_IF_SELECTION_POS 11
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#define FAR_END_LOOPBACK_MODE_MASK 0x0008
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#define MII_VSC85XX_INT_MASK 25
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#define MII_VSC85XX_INT_MASK_MASK 0xa000
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#define MII_VSC85XX_INT_MASK_WOL 0x0040
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#define MII_VSC85XX_INT_STATUS 26
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#define MSCC_PHY_WOL_MAC_CONTROL 27
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#define EDGE_RATE_CNTL_POS 5
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#define EDGE_RATE_CNTL_MASK 0x00E0
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#define MSCC_PHY_DEV_AUX_CNTL 28
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#define HP_AUTO_MDIX_X_OVER_IND_MASK 0x2000
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#define MSCC_PHY_LED_MODE_SEL 29
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#define LED_MODE_SEL_POS(x) ((x) * 4)
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#define LED_MODE_SEL_MASK(x) (GENMASK(3, 0) << LED_MODE_SEL_POS(x))
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#define LED_MODE_SEL(x, mode) (((mode) << LED_MODE_SEL_POS(x)) & LED_MODE_SEL_MASK(x))
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#define MSCC_EXT_PAGE_ACCESS 31
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#define MSCC_PHY_PAGE_STANDARD 0x0000 /* Standard registers */
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#define MSCC_PHY_PAGE_EXTENDED 0x0001 /* Extended registers */
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#define MSCC_PHY_PAGE_EXTENDED_2 0x0002 /* Extended reg - page 2 */
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/* Extended Page 1 Registers */
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#define MSCC_PHY_EXT_MODE_CNTL 19
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#define FORCE_MDI_CROSSOVER_MASK 0x000C
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#define FORCE_MDI_CROSSOVER_MDIX 0x000C
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#define FORCE_MDI_CROSSOVER_MDI 0x0008
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#define MSCC_PHY_ACTIPHY_CNTL 20
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#define DOWNSHIFT_CNTL_MASK 0x001C
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#define DOWNSHIFT_EN 0x0010
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#define DOWNSHIFT_CNTL_POS 2
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/* Extended Page 2 Registers */
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#define MSCC_PHY_RGMII_CNTL 20
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#define RGMII_RX_CLK_DELAY_MASK 0x0070
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#define RGMII_RX_CLK_DELAY_POS 4
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#define MSCC_PHY_WOL_LOWER_MAC_ADDR 21
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#define MSCC_PHY_WOL_MID_MAC_ADDR 22
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#define MSCC_PHY_WOL_UPPER_MAC_ADDR 23
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#define MSCC_PHY_WOL_LOWER_PASSWD 24
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#define MSCC_PHY_WOL_MID_PASSWD 25
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#define MSCC_PHY_WOL_UPPER_PASSWD 26
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#define MSCC_PHY_WOL_MAC_CONTROL 27
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#define SECURE_ON_ENABLE 0x8000
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#define SECURE_ON_PASSWD_LEN_4 0x4000
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/* Microsemi PHY ID's */
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#define PHY_ID_VSC8530 0x00070560
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#define PHY_ID_VSC8531 0x00070570
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#define PHY_ID_VSC8540 0x00070760
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#define PHY_ID_VSC8541 0x00070770
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#define MSCC_VDDMAC_1500 1500
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#define MSCC_VDDMAC_1800 1800
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#define MSCC_VDDMAC_2500 2500
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#define MSCC_VDDMAC_3300 3300
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#define DOWNSHIFT_COUNT_MAX 5
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#define MAX_LEDS 4
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#define VSC85XX_SUPP_LED_MODES (BIT(VSC8531_LINK_ACTIVITY) | \
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BIT(VSC8531_LINK_1000_ACTIVITY) | \
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BIT(VSC8531_LINK_100_ACTIVITY) | \
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BIT(VSC8531_LINK_10_ACTIVITY) | \
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BIT(VSC8531_LINK_100_1000_ACTIVITY) | \
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BIT(VSC8531_LINK_10_1000_ACTIVITY) | \
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BIT(VSC8531_LINK_10_100_ACTIVITY) | \
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BIT(VSC8531_DUPLEX_COLLISION) | \
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BIT(VSC8531_COLLISION) | \
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BIT(VSC8531_ACTIVITY) | \
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BIT(VSC8531_AUTONEG_FAULT) | \
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BIT(VSC8531_SERIAL_MODE) | \
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BIT(VSC8531_FORCE_LED_OFF) | \
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BIT(VSC8531_FORCE_LED_ON))
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struct vsc8531_private {
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int rate_magic;
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u16 supp_led_modes;
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u32 leds_mode[MAX_LEDS];
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u8 nleds;
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};
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#ifdef CONFIG_OF_MDIO
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struct vsc8531_edge_rate_table {
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u32 vddmac;
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u32 slowdown[8];
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};
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static const struct vsc8531_edge_rate_table edge_table[] = {
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{MSCC_VDDMAC_3300, { 0, 2, 4, 7, 10, 17, 29, 53} },
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{MSCC_VDDMAC_2500, { 0, 3, 6, 10, 14, 23, 37, 63} },
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{MSCC_VDDMAC_1800, { 0, 5, 9, 16, 23, 35, 52, 76} },
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{MSCC_VDDMAC_1500, { 0, 6, 14, 21, 29, 42, 58, 77} },
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};
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#endif /* CONFIG_OF_MDIO */
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static int vsc85xx_phy_read_page(struct phy_device *phydev)
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{
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return __phy_read(phydev, MSCC_EXT_PAGE_ACCESS);
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}
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static int vsc85xx_phy_write_page(struct phy_device *phydev, int page)
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{
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return __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page);
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}
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static int vsc85xx_led_cntl_set(struct phy_device *phydev,
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u8 led_num,
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u8 mode)
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{
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int rc;
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u16 reg_val;
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mutex_lock(&phydev->lock);
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reg_val = phy_read(phydev, MSCC_PHY_LED_MODE_SEL);
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reg_val &= ~LED_MODE_SEL_MASK(led_num);
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reg_val |= LED_MODE_SEL(led_num, (u16)mode);
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rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val);
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mutex_unlock(&phydev->lock);
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return rc;
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}
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static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix)
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{
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u16 reg_val;
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reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL);
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if (reg_val & HP_AUTO_MDIX_X_OVER_IND_MASK)
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*mdix = ETH_TP_MDI_X;
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else
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*mdix = ETH_TP_MDI;
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return 0;
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}
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static int vsc85xx_mdix_set(struct phy_device *phydev, u8 mdix)
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{
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int rc;
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u16 reg_val;
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reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL);
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if ((mdix == ETH_TP_MDI) || (mdix == ETH_TP_MDI_X)) {
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reg_val |= (DISABLE_PAIR_SWAP_CORR_MASK |
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DISABLE_POLARITY_CORR_MASK |
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DISABLE_HP_AUTO_MDIX_MASK);
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} else {
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reg_val &= ~(DISABLE_PAIR_SWAP_CORR_MASK |
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DISABLE_POLARITY_CORR_MASK |
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DISABLE_HP_AUTO_MDIX_MASK);
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}
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rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val);
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if (rc != 0)
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return rc;
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reg_val = 0;
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if (mdix == ETH_TP_MDI)
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reg_val = FORCE_MDI_CROSSOVER_MDI;
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else if (mdix == ETH_TP_MDI_X)
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reg_val = FORCE_MDI_CROSSOVER_MDIX;
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rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
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MSCC_PHY_EXT_MODE_CNTL, FORCE_MDI_CROSSOVER_MASK,
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reg_val);
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if (rc < 0)
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return rc;
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return genphy_restart_aneg(phydev);
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}
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static int vsc85xx_downshift_get(struct phy_device *phydev, u8 *count)
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{
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u16 reg_val;
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reg_val = phy_read_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
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MSCC_PHY_ACTIPHY_CNTL);
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if (reg_val < 0)
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return reg_val;
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reg_val &= DOWNSHIFT_CNTL_MASK;
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if (!(reg_val & DOWNSHIFT_EN))
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*count = DOWNSHIFT_DEV_DISABLE;
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else
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*count = ((reg_val & ~DOWNSHIFT_EN) >> DOWNSHIFT_CNTL_POS) + 2;
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return 0;
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}
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static int vsc85xx_downshift_set(struct phy_device *phydev, u8 count)
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{
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if (count == DOWNSHIFT_DEV_DEFAULT_COUNT) {
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/* Default downshift count 3 (i.e. Bit3:2 = 0b01) */
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count = ((1 << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN);
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} else if (count > DOWNSHIFT_COUNT_MAX || count == 1) {
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phydev_err(phydev, "Downshift count should be 2,3,4 or 5\n");
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return -ERANGE;
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} else if (count) {
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/* Downshift count is either 2,3,4 or 5 */
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count = (((count - 2) << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN);
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}
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return phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
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MSCC_PHY_ACTIPHY_CNTL, DOWNSHIFT_CNTL_MASK,
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count);
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}
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static int vsc85xx_wol_set(struct phy_device *phydev,
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struct ethtool_wolinfo *wol)
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{
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int rc;
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u16 reg_val;
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u8 i;
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u16 pwd[3] = {0, 0, 0};
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struct ethtool_wolinfo *wol_conf = wol;
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u8 *mac_addr = phydev->attached_dev->dev_addr;
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mutex_lock(&phydev->lock);
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rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2);
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if (rc < 0) {
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rc = phy_restore_page(phydev, rc, rc);
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goto out_unlock;
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}
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if (wol->wolopts & WAKE_MAGIC) {
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/* Store the device address for the magic packet */
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for (i = 0; i < ARRAY_SIZE(pwd); i++)
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pwd[i] = mac_addr[5 - (i * 2 + 1)] << 8 |
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mac_addr[5 - i * 2];
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__phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]);
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__phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, pwd[1]);
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__phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, pwd[2]);
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} else {
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__phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0);
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__phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0);
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__phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0);
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}
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if (wol_conf->wolopts & WAKE_MAGICSECURE) {
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for (i = 0; i < ARRAY_SIZE(pwd); i++)
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pwd[i] = wol_conf->sopass[5 - (i * 2 + 1)] << 8 |
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wol_conf->sopass[5 - i * 2];
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__phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]);
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__phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, pwd[1]);
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__phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, pwd[2]);
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} else {
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__phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0);
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__phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0);
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__phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0);
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}
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reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
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if (wol_conf->wolopts & WAKE_MAGICSECURE)
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reg_val |= SECURE_ON_ENABLE;
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else
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reg_val &= ~SECURE_ON_ENABLE;
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__phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val);
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rc = phy_restore_page(phydev, rc, rc > 0 ? 0 : rc);
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if (rc < 0)
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goto out_unlock;
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if (wol->wolopts & WAKE_MAGIC) {
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/* Enable the WOL interrupt */
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reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
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reg_val |= MII_VSC85XX_INT_MASK_WOL;
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rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
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if (rc != 0)
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goto out_unlock;
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} else {
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/* Disable the WOL interrupt */
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reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
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reg_val &= (~MII_VSC85XX_INT_MASK_WOL);
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rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
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if (rc != 0)
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goto out_unlock;
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}
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/* Clear WOL iterrupt status */
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reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS);
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out_unlock:
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mutex_unlock(&phydev->lock);
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return rc;
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}
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static void vsc85xx_wol_get(struct phy_device *phydev,
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struct ethtool_wolinfo *wol)
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{
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int rc;
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u16 reg_val;
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u8 i;
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u16 pwd[3] = {0, 0, 0};
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struct ethtool_wolinfo *wol_conf = wol;
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mutex_lock(&phydev->lock);
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rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2);
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if (rc < 0)
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goto out_unlock;
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reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
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if (reg_val & SECURE_ON_ENABLE)
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wol_conf->wolopts |= WAKE_MAGICSECURE;
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if (wol_conf->wolopts & WAKE_MAGICSECURE) {
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pwd[0] = __phy_read(phydev, MSCC_PHY_WOL_LOWER_PASSWD);
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pwd[1] = __phy_read(phydev, MSCC_PHY_WOL_MID_PASSWD);
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pwd[2] = __phy_read(phydev, MSCC_PHY_WOL_UPPER_PASSWD);
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for (i = 0; i < ARRAY_SIZE(pwd); i++) {
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wol_conf->sopass[5 - i * 2] = pwd[i] & 0x00ff;
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wol_conf->sopass[5 - (i * 2 + 1)] = (pwd[i] & 0xff00)
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>> 8;
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}
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}
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out_unlock:
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phy_restore_page(phydev, rc, rc > 0 ? 0 : rc);
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mutex_unlock(&phydev->lock);
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}
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#ifdef CONFIG_OF_MDIO
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static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
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{
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u32 vdd, sd;
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int rc, i, j;
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struct device *dev = &phydev->mdio.dev;
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struct device_node *of_node = dev->of_node;
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u8 sd_array_size = ARRAY_SIZE(edge_table[0].slowdown);
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if (!of_node)
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return -ENODEV;
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rc = of_property_read_u32(of_node, "vsc8531,vddmac", &vdd);
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if (rc != 0)
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vdd = MSCC_VDDMAC_3300;
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rc = of_property_read_u32(of_node, "vsc8531,edge-slowdown", &sd);
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if (rc != 0)
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sd = 0;
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for (i = 0; i < ARRAY_SIZE(edge_table); i++)
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if (edge_table[i].vddmac == vdd)
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for (j = 0; j < sd_array_size; j++)
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if (edge_table[i].slowdown[j] == sd)
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return (sd_array_size - j - 1);
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return -EINVAL;
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}
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static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
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char *led,
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u32 default_mode)
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{
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struct vsc8531_private *priv = phydev->priv;
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struct device *dev = &phydev->mdio.dev;
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struct device_node *of_node = dev->of_node;
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u32 led_mode;
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int err;
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if (!of_node)
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return -ENODEV;
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led_mode = default_mode;
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err = of_property_read_u32(of_node, led, &led_mode);
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if (!err && !(BIT(led_mode) & priv->supp_led_modes)) {
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phydev_err(phydev, "DT %s invalid\n", led);
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return -EINVAL;
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}
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return led_mode;
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}
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#else
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static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
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{
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return 0;
|
|
}
|
|
|
|
static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
|
|
char *led,
|
|
u8 default_mode)
|
|
{
|
|
return default_mode;
|
|
}
|
|
#endif /* CONFIG_OF_MDIO */
|
|
|
|
static int vsc85xx_dt_led_modes_get(struct phy_device *phydev,
|
|
u32 *default_mode)
|
|
{
|
|
struct vsc8531_private *priv = phydev->priv;
|
|
char led_dt_prop[28];
|
|
int i, ret;
|
|
|
|
for (i = 0; i < priv->nleds; i++) {
|
|
ret = sprintf(led_dt_prop, "vsc8531,led-%d-mode", i);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = vsc85xx_dt_led_mode_get(phydev, led_dt_prop,
|
|
default_mode[i]);
|
|
if (ret < 0)
|
|
return ret;
|
|
priv->leds_mode[i] = ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 edge_rate)
|
|
{
|
|
int rc;
|
|
|
|
mutex_lock(&phydev->lock);
|
|
rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
|
|
MSCC_PHY_WOL_MAC_CONTROL, EDGE_RATE_CNTL_MASK,
|
|
edge_rate << EDGE_RATE_CNTL_POS);
|
|
mutex_unlock(&phydev->lock);
|
|
|
|
return rc;
|
|
}
|
|
|
|
static int vsc85xx_mac_if_set(struct phy_device *phydev,
|
|
phy_interface_t interface)
|
|
{
|
|
int rc;
|
|
u16 reg_val;
|
|
|
|
mutex_lock(&phydev->lock);
|
|
reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
|
|
reg_val &= ~(MAC_IF_SELECTION_MASK);
|
|
switch (interface) {
|
|
case PHY_INTERFACE_MODE_RGMII:
|
|
reg_val |= (MAC_IF_SELECTION_RGMII << MAC_IF_SELECTION_POS);
|
|
break;
|
|
case PHY_INTERFACE_MODE_RMII:
|
|
reg_val |= (MAC_IF_SELECTION_RMII << MAC_IF_SELECTION_POS);
|
|
break;
|
|
case PHY_INTERFACE_MODE_MII:
|
|
case PHY_INTERFACE_MODE_GMII:
|
|
reg_val |= (MAC_IF_SELECTION_GMII << MAC_IF_SELECTION_POS);
|
|
break;
|
|
default:
|
|
rc = -EINVAL;
|
|
goto out_unlock;
|
|
}
|
|
rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val);
|
|
if (rc != 0)
|
|
goto out_unlock;
|
|
|
|
rc = genphy_soft_reset(phydev);
|
|
|
|
out_unlock:
|
|
mutex_unlock(&phydev->lock);
|
|
|
|
return rc;
|
|
}
|
|
|
|
static int vsc85xx_default_config(struct phy_device *phydev)
|
|
{
|
|
int rc;
|
|
u16 reg_val;
|
|
|
|
phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
|
|
mutex_lock(&phydev->lock);
|
|
rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2);
|
|
if (rc < 0)
|
|
goto out_unlock;
|
|
|
|
reg_val = phy_read(phydev, MSCC_PHY_RGMII_CNTL);
|
|
reg_val &= ~(RGMII_RX_CLK_DELAY_MASK);
|
|
reg_val |= (RGMII_RX_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS);
|
|
phy_write(phydev, MSCC_PHY_RGMII_CNTL, reg_val);
|
|
|
|
out_unlock:
|
|
rc = phy_restore_page(phydev, rc, rc > 0 ? 0 : rc);
|
|
mutex_unlock(&phydev->lock);
|
|
|
|
return rc;
|
|
}
|
|
|
|
static int vsc85xx_get_tunable(struct phy_device *phydev,
|
|
struct ethtool_tunable *tuna, void *data)
|
|
{
|
|
switch (tuna->id) {
|
|
case ETHTOOL_PHY_DOWNSHIFT:
|
|
return vsc85xx_downshift_get(phydev, (u8 *)data);
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
static int vsc85xx_set_tunable(struct phy_device *phydev,
|
|
struct ethtool_tunable *tuna,
|
|
const void *data)
|
|
{
|
|
switch (tuna->id) {
|
|
case ETHTOOL_PHY_DOWNSHIFT:
|
|
return vsc85xx_downshift_set(phydev, *(u8 *)data);
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
static int vsc85xx_config_init(struct phy_device *phydev)
|
|
{
|
|
int rc, i;
|
|
struct vsc8531_private *vsc8531 = phydev->priv;
|
|
|
|
rc = vsc85xx_default_config(phydev);
|
|
if (rc)
|
|
return rc;
|
|
|
|
rc = vsc85xx_mac_if_set(phydev, phydev->interface);
|
|
if (rc)
|
|
return rc;
|
|
|
|
rc = vsc85xx_edge_rate_cntl_set(phydev, vsc8531->rate_magic);
|
|
if (rc)
|
|
return rc;
|
|
|
|
for (i = 0; i < vsc8531->nleds; i++) {
|
|
rc = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
|
|
if (rc)
|
|
return rc;
|
|
}
|
|
|
|
rc = genphy_config_init(phydev);
|
|
|
|
return rc;
|
|
}
|
|
|
|
static int vsc85xx_ack_interrupt(struct phy_device *phydev)
|
|
{
|
|
int rc = 0;
|
|
|
|
if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
|
|
rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
|
|
|
|
return (rc < 0) ? rc : 0;
|
|
}
|
|
|
|
static int vsc85xx_config_intr(struct phy_device *phydev)
|
|
{
|
|
int rc;
|
|
|
|
if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
|
|
rc = phy_write(phydev, MII_VSC85XX_INT_MASK,
|
|
MII_VSC85XX_INT_MASK_MASK);
|
|
} else {
|
|
rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0);
|
|
if (rc < 0)
|
|
return rc;
|
|
rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
|
|
}
|
|
|
|
return rc;
|
|
}
|
|
|
|
static int vsc85xx_config_aneg(struct phy_device *phydev)
|
|
{
|
|
int rc;
|
|
|
|
rc = vsc85xx_mdix_set(phydev, phydev->mdix_ctrl);
|
|
if (rc < 0)
|
|
return rc;
|
|
|
|
return genphy_config_aneg(phydev);
|
|
}
|
|
|
|
static int vsc85xx_read_status(struct phy_device *phydev)
|
|
{
|
|
int rc;
|
|
|
|
rc = vsc85xx_mdix_get(phydev, &phydev->mdix);
|
|
if (rc < 0)
|
|
return rc;
|
|
|
|
return genphy_read_status(phydev);
|
|
}
|
|
|
|
static int vsc85xx_probe(struct phy_device *phydev)
|
|
{
|
|
struct vsc8531_private *vsc8531;
|
|
int rate_magic;
|
|
u32 default_mode[2] = {VSC8531_LINK_1000_ACTIVITY,
|
|
VSC8531_LINK_100_ACTIVITY};
|
|
|
|
rate_magic = vsc85xx_edge_rate_magic_get(phydev);
|
|
if (rate_magic < 0)
|
|
return rate_magic;
|
|
|
|
vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
|
|
if (!vsc8531)
|
|
return -ENOMEM;
|
|
|
|
phydev->priv = vsc8531;
|
|
|
|
vsc8531->rate_magic = rate_magic;
|
|
vsc8531->nleds = 2;
|
|
vsc8531->supp_led_modes = VSC85XX_SUPP_LED_MODES;
|
|
|
|
return vsc85xx_dt_led_modes_get(phydev, default_mode);
|
|
}
|
|
|
|
/* Microsemi VSC85xx PHYs */
|
|
static struct phy_driver vsc85xx_driver[] = {
|
|
{
|
|
.phy_id = PHY_ID_VSC8530,
|
|
.name = "Microsemi FE VSC8530",
|
|
.phy_id_mask = 0xfffffff0,
|
|
.features = PHY_BASIC_FEATURES,
|
|
.flags = PHY_HAS_INTERRUPT,
|
|
.soft_reset = &genphy_soft_reset,
|
|
.config_init = &vsc85xx_config_init,
|
|
.config_aneg = &vsc85xx_config_aneg,
|
|
.aneg_done = &genphy_aneg_done,
|
|
.read_status = &vsc85xx_read_status,
|
|
.ack_interrupt = &vsc85xx_ack_interrupt,
|
|
.config_intr = &vsc85xx_config_intr,
|
|
.suspend = &genphy_suspend,
|
|
.resume = &genphy_resume,
|
|
.probe = &vsc85xx_probe,
|
|
.set_wol = &vsc85xx_wol_set,
|
|
.get_wol = &vsc85xx_wol_get,
|
|
.get_tunable = &vsc85xx_get_tunable,
|
|
.set_tunable = &vsc85xx_set_tunable,
|
|
.read_page = &vsc85xx_phy_read_page,
|
|
.write_page = &vsc85xx_phy_write_page,
|
|
},
|
|
{
|
|
.phy_id = PHY_ID_VSC8531,
|
|
.name = "Microsemi VSC8531",
|
|
.phy_id_mask = 0xfffffff0,
|
|
.features = PHY_GBIT_FEATURES,
|
|
.flags = PHY_HAS_INTERRUPT,
|
|
.soft_reset = &genphy_soft_reset,
|
|
.config_init = &vsc85xx_config_init,
|
|
.config_aneg = &vsc85xx_config_aneg,
|
|
.aneg_done = &genphy_aneg_done,
|
|
.read_status = &vsc85xx_read_status,
|
|
.ack_interrupt = &vsc85xx_ack_interrupt,
|
|
.config_intr = &vsc85xx_config_intr,
|
|
.suspend = &genphy_suspend,
|
|
.resume = &genphy_resume,
|
|
.probe = &vsc85xx_probe,
|
|
.set_wol = &vsc85xx_wol_set,
|
|
.get_wol = &vsc85xx_wol_get,
|
|
.get_tunable = &vsc85xx_get_tunable,
|
|
.set_tunable = &vsc85xx_set_tunable,
|
|
.read_page = &vsc85xx_phy_read_page,
|
|
.write_page = &vsc85xx_phy_write_page,
|
|
},
|
|
{
|
|
.phy_id = PHY_ID_VSC8540,
|
|
.name = "Microsemi FE VSC8540 SyncE",
|
|
.phy_id_mask = 0xfffffff0,
|
|
.features = PHY_BASIC_FEATURES,
|
|
.flags = PHY_HAS_INTERRUPT,
|
|
.soft_reset = &genphy_soft_reset,
|
|
.config_init = &vsc85xx_config_init,
|
|
.config_aneg = &vsc85xx_config_aneg,
|
|
.aneg_done = &genphy_aneg_done,
|
|
.read_status = &vsc85xx_read_status,
|
|
.ack_interrupt = &vsc85xx_ack_interrupt,
|
|
.config_intr = &vsc85xx_config_intr,
|
|
.suspend = &genphy_suspend,
|
|
.resume = &genphy_resume,
|
|
.probe = &vsc85xx_probe,
|
|
.set_wol = &vsc85xx_wol_set,
|
|
.get_wol = &vsc85xx_wol_get,
|
|
.get_tunable = &vsc85xx_get_tunable,
|
|
.set_tunable = &vsc85xx_set_tunable,
|
|
.read_page = &vsc85xx_phy_read_page,
|
|
.write_page = &vsc85xx_phy_write_page,
|
|
},
|
|
{
|
|
.phy_id = PHY_ID_VSC8541,
|
|
.name = "Microsemi VSC8541 SyncE",
|
|
.phy_id_mask = 0xfffffff0,
|
|
.features = PHY_GBIT_FEATURES,
|
|
.flags = PHY_HAS_INTERRUPT,
|
|
.soft_reset = &genphy_soft_reset,
|
|
.config_init = &vsc85xx_config_init,
|
|
.config_aneg = &vsc85xx_config_aneg,
|
|
.aneg_done = &genphy_aneg_done,
|
|
.read_status = &vsc85xx_read_status,
|
|
.ack_interrupt = &vsc85xx_ack_interrupt,
|
|
.config_intr = &vsc85xx_config_intr,
|
|
.suspend = &genphy_suspend,
|
|
.resume = &genphy_resume,
|
|
.probe = &vsc85xx_probe,
|
|
.set_wol = &vsc85xx_wol_set,
|
|
.get_wol = &vsc85xx_wol_get,
|
|
.get_tunable = &vsc85xx_get_tunable,
|
|
.set_tunable = &vsc85xx_set_tunable,
|
|
.read_page = &vsc85xx_phy_read_page,
|
|
.write_page = &vsc85xx_phy_write_page,
|
|
}
|
|
|
|
};
|
|
|
|
module_phy_driver(vsc85xx_driver);
|
|
|
|
static struct mdio_device_id __maybe_unused vsc85xx_tbl[] = {
|
|
{ PHY_ID_VSC8530, 0xfffffff0, },
|
|
{ PHY_ID_VSC8531, 0xfffffff0, },
|
|
{ PHY_ID_VSC8540, 0xfffffff0, },
|
|
{ PHY_ID_VSC8541, 0xfffffff0, },
|
|
{ }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(mdio, vsc85xx_tbl);
|
|
|
|
MODULE_DESCRIPTION("Microsemi VSC85xx PHY driver");
|
|
MODULE_AUTHOR("Nagaraju Lakkaraju");
|
|
MODULE_LICENSE("Dual MIT/GPL");
|