Jerome Brunet 69d9229327 clk: meson: add the gxl hdmi pll ... The hdmi pll used in the gxl family is actually different from the gxbb one. The register layout is completely different, which explain why the hdmi pll rate has always been rubbish on the gxl family. Adding the correct register field is the first part of the fix to get a correct rate out the hdmi pll Fixes: 0d48fc558d ("clk: meson-gxbb: Add GXL/GXM GP0 Variant") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>		2018-02-12 09:49:23 +01:00
..
axg.c	clk: meson: remove useless pll rate params tables	2018-02-12 09:49:22 +01:00
axg.h	clk: meson-axg: add clock controller drivers	2017-12-14 10:19:37 +01:00
clk-audio-divider.c	clk: meson: add audio clock divider support	2017-04-07 16:50:44 +02:00
clk-cpu.c	clk: meson8b: clean up cpu clocks	2016-06-22 18:02:35 -07:00
clk-mpll.c	clk: meson: mpll: use 64-bit maths in params_from_rate	2017-12-23 23:14:20 +01:00
clk-pll.c	clk: meson: add od3 to the pll driver	2018-02-12 09:49:23 +01:00
clkc.h	clk: meson: add od3 to the pll driver	2018-02-12 09:49:23 +01:00
gxbb-aoclk-32k.c	clk: meson: gxbb-aoclk: Add CEC 32k clock	2017-08-04 18:02:02 +02:00
gxbb-aoclk-regmap.c	clk: meson: gxbb-aoclk: Switch to regmap for register access	2017-08-04 18:02:01 +02:00
gxbb-aoclk.c	clk: meson: gxbb-aoclk: Add CEC 32k clock	2017-08-04 18:02:02 +02:00
gxbb-aoclk.h	clk: meson: gxbb-aoclk: Add CEC 32k clock	2017-08-04 18:02:02 +02:00
gxbb.c	clk: meson: add the gxl hdmi pll	2018-02-12 09:49:23 +01:00
gxbb.h	clk: meson: gxbb: Add VPU and VAPB clockids	2017-10-20 10:24:30 +02:00
Kconfig	clk: meson-axg: add clock controller drivers	2017-12-14 10:19:37 +01:00
Makefile	clk: meson-axg: add clock controller drivers	2017-12-14 10:19:37 +01:00
meson8b.c	clk: meson: make the spinlock naming more specific	2017-12-14 10:12:41 +01:00
meson8b.h	clk: meson: meson8b: register the built-in reset controller	2017-08-04 18:01:58 +02:00