forked from Minki/linux
c0d6fe2f01
As usual, this is the massive branch we have for each release. Lots of various updates and additions of hardware descriptions on existing hardware, as well as the usual additions of new boards and SoCs. This is also the first release where we've started mixing 64- and 32-bit DT updates in one branch. (Specific details on what's actually here and new is pretty easy to tell from the diffstat, so there's little point in duplicating listing it here.) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJWQT2WAAoJEIwa5zzehBx37tgQAIBe5eDJFXFihTlyOQ2plL3q vVH4OCzXIHELfM1J8CGZNah1wCQqNOts8RAmDCzxr+zSYuLOwJOEDZ6NKmErMxl0 NTj3+BsqKO3NRym970ofPqU9JRLQmpZ8K7dzk8Nwj2+r1WZHFu/j6Jv44n/Ns0lw 7+wxnG322lTm7SnvALCMD5lD4Y7VpThooWy5SdFtRoAetn+cLbVCJIeeQvO6Vxkp NooeJR0t2e8cpbAND5Jwu6eeWRcIbrvgjYDe0omhrIY05i9yNvIsC2HuQFGjF43z p2CnQvcKnhOXTZw3yse1Fx5igA7jqwVjjC/lVeDyxhusAtLpmuB6qbSaj7DpqkSQ nJxX1d49WKm68K+aknmee1kYRrvc4DE/kORI4IxXnsVNMu16ifTVLnxKgUhwzukb eZdTP6rsqgNozaYvh0k1vfSFd+CNSkBg+E9nrI3tU95yo3LOIhobVBCvBcWlmUvQ JdavRztqosChjIx3a9i1eCNKJtCg9p4m+gWjUqVVWsxBHe/3HojzjZnsBSynIQMA uGIVm0TKhNl1Svxl3oJo9257UCUK7+5PqJHK9IHrcWDULYx05JGSjuZcyvNS6Fo+ u1DMf0ud4gXJYhecFBa7b3zRjk5YxptgCCTjeEEOTUJbbhZqDjGFZlNuFi6dmqD3 ILJ2QMe/DGiPIlUmCfsx =qY1q -----END PGP SIGNATURE----- Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Olof Johansson: "As usual, this is the massive branch we have for each release. Lots of various updates and additions of hardware descriptions on existing hardware, as well as the usual additions of new boards and SoCs. This is also the first release where we've started mixing 64- and 32-bit DT updates in one branch. (Specific details on what's actually here and new is pretty easy to tell from the diffstat, so there's little point in duplicating listing it here)" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (499 commits) ARM: dts: uniphier: add system-bus-controller nodes ARM64: juno: disable NOR flash node by default ARM: dts: uniphier: add outer cache controller nodes arm64: defconfig: Enable PCI generic host bridge by default arm64: Juno: Add support for the PCIe host bridge on Juno R1 Documentation: of: Document the bindings used by Juno R1 PCIe host bridge ARM: dts: uniphier: add I2C aliases for ProXstream2 boards dts/Makefile: Add build support for LS2080a QDS & RDB board DTS dts/ls2080a: Add DTS support for LS2080a QDS & RDB boards dts/ls2080a: Update Simulator DTS to add support of various peripherals dts/ls2080a: Remove text about writing to Free Software Foundation dts/ls2080a: Update DTSI to add support of various peripherals doc: DTS: Update DWC3 binding to provide reference to generic bindings doc/bindings: Update GPIO devicetree binding documentation for LS2080A Documentation/dts: Move FSL board-specific bindings out of /powerpc Documentation: DT: Add entry for FSL LS2080A QDS and RDB boards arm64: Rename FSL LS2085A SoC support code to LS2080A arm64: Use generic Layerscape SoC family naming ARM: dts: uniphier: add ProXstream2 Vodka board support ARM: dts: uniphier: add ProXstream2 Gentil board support ...
1089 lines
24 KiB
Plaintext
1089 lines
24 KiB
Plaintext
/*
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* sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
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*
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* Copyright (C) 2015 Atmel,
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* 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/dma/at91.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/clock/at91.h>
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/ {
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model = "Atmel SAMA5D2 family SoC";
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compatible = "atmel,sama5d2";
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interrupt-parent = <&aic>;
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aliases {
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serial0 = &uart1;
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serial1 = &uart3;
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tcb0 = &tcb0;
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tcb1 = &tcb1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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reg = <0>;
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next-level-cache = <&L2>;
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};
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};
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memory {
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reg = <0x20000000 0x20000000>;
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};
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clocks {
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slow_xtal: slow_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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main_xtal: main_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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adc_op_clk: adc_op_clk{
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <1000000>;
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};
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};
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ns_sram: sram@00200000 {
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compatible = "mmio-sram";
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reg = <0x00200000 0x20000>;
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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usb0: gadget@00300000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "atmel,sama5d3-udc";
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reg = <0x00300000 0x100000
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0xfc02c000 0x400>;
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interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
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clocks = <&udphs_clk>, <&utmi>;
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clock-names = "pclk", "hclk";
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status = "disabled";
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ep0 {
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reg = <0>;
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atmel,fifo-size = <64>;
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atmel,nb-banks = <1>;
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};
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ep1 {
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reg = <1>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <3>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep2 {
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reg = <2>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <3>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep3 {
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reg = <3>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep4 {
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reg = <4>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep5 {
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reg = <5>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep6 {
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reg = <6>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep7 {
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reg = <7>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep8 {
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reg = <8>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep9 {
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reg = <9>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep10 {
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reg = <10>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep11 {
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reg = <11>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep12 {
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reg = <12>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep13 {
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reg = <13>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep14 {
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reg = <14>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep15 {
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reg = <15>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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};
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usb1: ohci@00400000 {
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compatible = "atmel,at91rm9200-ohci", "usb-ohci";
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reg = <0x00400000 0x100000>;
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interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
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clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
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clock-names = "ohci_clk", "hclk", "uhpck";
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status = "disabled";
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};
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usb2: ehci@00500000 {
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compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
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reg = <0x00500000 0x100000>;
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interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
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clocks = <&utmi>, <&uhphs_clk>;
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clock-names = "usb_clk", "ehci_clk";
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status = "disabled";
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};
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L2: cache-controller@00a00000 {
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compatible = "arm,pl310-cache";
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reg = <0x00a00000 0x1000>;
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interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
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cache-unified;
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cache-level = <2>;
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};
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sdmmc0: sdio-host@a0000000 {
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compatible = "atmel,sama5d2-sdhci";
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reg = <0xa0000000 0x300>;
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interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
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clock-names = "hclock", "multclk", "baseclk";
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status = "disabled";
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};
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sdmmc1: sdio-host@b0000000 {
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compatible = "atmel,sama5d2-sdhci";
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reg = <0xb0000000 0x300>;
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interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
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clock-names = "hclock", "multclk", "baseclk";
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status = "disabled";
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};
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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ramc0: ramc@f000c000 {
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compatible = "atmel,sama5d3-ddramc";
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reg = <0xf000c000 0x200>;
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clocks = <&ddrck>, <&mpddr_clk>;
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clock-names = "ddrck", "mpddr";
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};
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dma0: dma-controller@f0010000 {
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compatible = "atmel,sama5d4-dma";
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reg = <0xf0010000 0x1000>;
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interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
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#dma-cells = <1>;
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clocks = <&dma0_clk>;
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clock-names = "dma_clk";
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};
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pmc: pmc@f0014000 {
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compatible = "atmel,sama5d2-pmc", "syscon";
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reg = <0xf0014000 0x160>;
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interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
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interrupt-controller;
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#address-cells = <1>;
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#size-cells = <0>;
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#interrupt-cells = <1>;
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main_rc_osc: main_rc_osc {
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compatible = "atmel,at91sam9x5-clk-main-rc-osc";
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#clock-cells = <0>;
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interrupt-parent = <&pmc>;
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interrupts = <AT91_PMC_MOSCRCS>;
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clock-frequency = <12000000>;
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clock-accuracy = <100000000>;
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};
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main_osc: main_osc {
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compatible = "atmel,at91rm9200-clk-main-osc";
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#clock-cells = <0>;
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interrupt-parent = <&pmc>;
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interrupts = <AT91_PMC_MOSCS>;
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clocks = <&main_xtal>;
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};
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main: mainck {
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compatible = "atmel,at91sam9x5-clk-main";
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#clock-cells = <0>;
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interrupt-parent = <&pmc>;
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interrupts = <AT91_PMC_MOSCSELS>;
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clocks = <&main_rc_osc &main_osc>;
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};
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plla: pllack {
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compatible = "atmel,sama5d3-clk-pll";
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#clock-cells = <0>;
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interrupt-parent = <&pmc>;
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interrupts = <AT91_PMC_LOCKA>;
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clocks = <&main>;
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reg = <0>;
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atmel,clk-input-range = <12000000 12000000>;
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#atmel,pll-clk-output-range-cells = <4>;
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atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
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};
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plladiv: plladivck {
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compatible = "atmel,at91sam9x5-clk-plldiv";
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#clock-cells = <0>;
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clocks = <&plla>;
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};
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utmi: utmick {
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compatible = "atmel,at91sam9x5-clk-utmi";
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#clock-cells = <0>;
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interrupt-parent = <&pmc>;
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interrupts = <AT91_PMC_LOCKU>;
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clocks = <&main>;
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};
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mck: masterck {
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compatible = "atmel,at91sam9x5-clk-master";
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#clock-cells = <0>;
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interrupt-parent = <&pmc>;
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interrupts = <AT91_PMC_MCKRDY>;
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clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
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atmel,clk-output-range = <124000000 166000000>;
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atmel,clk-divisors = <1 2 4 3>;
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};
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h32ck: h32mxck {
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#clock-cells = <0>;
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compatible = "atmel,sama5d4-clk-h32mx";
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clocks = <&mck>;
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};
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usb: usbck {
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compatible = "atmel,at91sam9x5-clk-usb";
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#clock-cells = <0>;
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clocks = <&plladiv>, <&utmi>;
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};
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prog: progck {
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compatible = "atmel,at91sam9x5-clk-programmable";
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&pmc>;
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clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
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prog0: prog0 {
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#clock-cells = <0>;
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reg = <0>;
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interrupts = <AT91_PMC_PCKRDY(0)>;
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};
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prog1: prog1 {
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#clock-cells = <0>;
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reg = <1>;
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interrupts = <AT91_PMC_PCKRDY(1)>;
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};
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prog2: prog2 {
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#clock-cells = <0>;
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reg = <2>;
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interrupts = <AT91_PMC_PCKRDY(2)>;
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};
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};
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systemck {
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compatible = "atmel,at91rm9200-clk-system";
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#address-cells = <1>;
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#size-cells = <0>;
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ddrck: ddrck {
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#clock-cells = <0>;
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reg = <2>;
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clocks = <&mck>;
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};
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lcdck: lcdck {
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#clock-cells = <0>;
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reg = <3>;
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clocks = <&mck>;
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};
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uhpck: uhpck {
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#clock-cells = <0>;
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reg = <6>;
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clocks = <&usb>;
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};
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udpck: udpck {
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#clock-cells = <0>;
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reg = <7>;
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clocks = <&usb>;
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};
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pck0: pck0 {
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#clock-cells = <0>;
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reg = <8>;
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clocks = <&prog0>;
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};
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pck1: pck1 {
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#clock-cells = <0>;
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reg = <9>;
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clocks = <&prog1>;
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};
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pck2: pck2 {
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#clock-cells = <0>;
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reg = <10>;
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clocks = <&prog2>;
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};
|
|
|
|
iscck: iscck {
|
|
#clock-cells = <0>;
|
|
reg = <18>;
|
|
clocks = <&mck>;
|
|
};
|
|
};
|
|
|
|
periph32ck {
|
|
compatible = "atmel,at91sam9x5-clk-peripheral";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&h32ck>;
|
|
|
|
macb0_clk: macb0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <5>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
tdes_clk: tdes_clk {
|
|
#clock-cells = <0>;
|
|
reg = <11>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
matrix1_clk: matrix1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <14>;
|
|
};
|
|
|
|
hsmc_clk: hsmc_clk {
|
|
#clock-cells = <0>;
|
|
reg = <17>;
|
|
};
|
|
|
|
pioA_clk: pioA_clk {
|
|
#clock-cells = <0>;
|
|
reg = <18>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
flx0_clk: flx0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <19>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
flx1_clk: flx1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <20>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
flx2_clk: flx2_clk {
|
|
#clock-cells = <0>;
|
|
reg = <21>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
flx3_clk: flx3_clk {
|
|
#clock-cells = <0>;
|
|
reg = <22>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
flx4_clk: flx4_clk {
|
|
#clock-cells = <0>;
|
|
reg = <23>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
uart0_clk: uart0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <24>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
uart1_clk: uart1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <25>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
uart2_clk: uart2_clk {
|
|
#clock-cells = <0>;
|
|
reg = <26>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
uart3_clk: uart3_clk {
|
|
#clock-cells = <0>;
|
|
reg = <27>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
uart4_clk: uart4_clk {
|
|
#clock-cells = <0>;
|
|
reg = <28>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
twi0_clk: twi0_clk {
|
|
reg = <29>;
|
|
#clock-cells = <0>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
twi1_clk: twi1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <30>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
spi0_clk: spi0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <33>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
spi1_clk: spi1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <34>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
tcb0_clk: tcb0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <35>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
tcb1_clk: tcb1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <36>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
pwm_clk: pwm_clk {
|
|
#clock-cells = <0>;
|
|
reg = <38>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
adc_clk: adc_clk {
|
|
#clock-cells = <0>;
|
|
reg = <40>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
uhphs_clk: uhphs_clk {
|
|
#clock-cells = <0>;
|
|
reg = <41>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
udphs_clk: udphs_clk {
|
|
#clock-cells = <0>;
|
|
reg = <42>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
ssc0_clk: ssc0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <43>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
ssc1_clk: ssc1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <44>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
trng_clk: trng_clk {
|
|
#clock-cells = <0>;
|
|
reg = <47>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
i2s0_clk: i2s0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <54>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
i2s1_clk: i2s1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <55>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
classd_clk: classd_clk {
|
|
#clock-cells = <0>;
|
|
reg = <59>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
};
|
|
|
|
periph64ck {
|
|
compatible = "atmel,at91sam9x5-clk-peripheral";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&mck>;
|
|
|
|
dma0_clk: dma0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <6>;
|
|
};
|
|
|
|
dma1_clk: dma1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <7>;
|
|
};
|
|
|
|
aes_clk: aes_clk {
|
|
#clock-cells = <0>;
|
|
reg = <9>;
|
|
};
|
|
|
|
aesb_clk: aesb_clk {
|
|
#clock-cells = <0>;
|
|
reg = <10>;
|
|
};
|
|
|
|
sha_clk: sha_clk {
|
|
#clock-cells = <0>;
|
|
reg = <12>;
|
|
};
|
|
|
|
mpddr_clk: mpddr_clk {
|
|
#clock-cells = <0>;
|
|
reg = <13>;
|
|
};
|
|
|
|
matrix0_clk: matrix0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <15>;
|
|
};
|
|
|
|
sdmmc0_hclk: sdmmc0_hclk {
|
|
#clock-cells = <0>;
|
|
reg = <31>;
|
|
};
|
|
|
|
sdmmc1_hclk: sdmmc1_hclk {
|
|
#clock-cells = <0>;
|
|
reg = <32>;
|
|
};
|
|
|
|
lcdc_clk: lcdc_clk {
|
|
#clock-cells = <0>;
|
|
reg = <45>;
|
|
};
|
|
|
|
isc_clk: isc_clk {
|
|
#clock-cells = <0>;
|
|
reg = <46>;
|
|
};
|
|
|
|
qspi0_clk: qspi0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <52>;
|
|
};
|
|
|
|
qspi1_clk: qspi1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <53>;
|
|
};
|
|
};
|
|
|
|
gck {
|
|
compatible = "atmel,sama5d2-clk-generated";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupt-parent = <&pmc>;
|
|
clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
|
|
|
|
sdmmc0_gclk: sdmmc0_gclk {
|
|
#clock-cells = <0>;
|
|
reg = <31>;
|
|
};
|
|
|
|
sdmmc1_gclk: sdmmc1_gclk {
|
|
#clock-cells = <0>;
|
|
reg = <32>;
|
|
};
|
|
|
|
tcb0_gclk: tcb0_gclk {
|
|
#clock-cells = <0>;
|
|
reg = <35>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
tcb1_gclk: tcb1_gclk {
|
|
#clock-cells = <0>;
|
|
reg = <36>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
pwm_gclk: pwm_gclk {
|
|
#clock-cells = <0>;
|
|
reg = <38>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
i2s0_gclk: i2s0_gclk {
|
|
#clock-cells = <0>;
|
|
reg = <54>;
|
|
};
|
|
|
|
i2s1_gclk: i2s1_gclk {
|
|
#clock-cells = <0>;
|
|
reg = <55>;
|
|
};
|
|
};
|
|
};
|
|
|
|
sha@f0028000 {
|
|
compatible = "atmel,at91sam9g46-sha";
|
|
reg = <0xf0028000 0x100>;
|
|
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(30))>;
|
|
dma-names = "tx";
|
|
clocks = <&sha_clk>;
|
|
clock-names = "sha_clk";
|
|
status = "okay";
|
|
};
|
|
|
|
aes@f002c000 {
|
|
compatible = "atmel,at91sam9g46-aes";
|
|
reg = <0xf002c000 0x100>;
|
|
interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(26))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(27))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&aes_clk>;
|
|
clock-names = "aes_clk";
|
|
status = "okay";
|
|
};
|
|
|
|
spi0: spi@f8000000 {
|
|
compatible = "atmel,at91rm9200-spi";
|
|
reg = <0xf8000000 0x100>;
|
|
interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(6))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(7))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&spi0_clk>;
|
|
clock-names = "spi_clk";
|
|
atmel,fifo-size = <16>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
macb0: ethernet@f8008000 {
|
|
compatible = "atmel,sama5d2-gem";
|
|
reg = <0xf8008000 0x1000>;
|
|
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */
|
|
66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */
|
|
67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&macb0_clk>, <&macb0_clk>;
|
|
clock-names = "hclk", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
tcb0: timer@f800c000 {
|
|
compatible = "atmel,at91sam9x5-tcb";
|
|
reg = <0xf800c000 0x100>;
|
|
interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&tcb0_clk>, <&clk32k>;
|
|
clock-names = "t0_clk", "slow_clk";
|
|
};
|
|
|
|
tcb1: timer@f8010000 {
|
|
compatible = "atmel,at91sam9x5-tcb";
|
|
reg = <0xf8010000 0x100>;
|
|
interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&tcb1_clk>, <&clk32k>;
|
|
clock-names = "t0_clk", "slow_clk";
|
|
};
|
|
|
|
uart0: serial@f801c000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xf801c000 0x100>;
|
|
interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
clocks = <&uart0_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@f8020000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xf8020000 0x100>;
|
|
interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
clocks = <&uart1_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@f8024000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xf8024000 0x100>;
|
|
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
clocks = <&uart2_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@f8028000 {
|
|
compatible = "atmel,sama5d2-i2c";
|
|
reg = <0xf8028000 0x100>;
|
|
interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(0))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(1))>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&twi0_clk>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flx0: flexcom@f8034000 {
|
|
compatible = "atmel,sama5d2-flexcom";
|
|
reg = <0xf8034000 0x200>;
|
|
clocks = <&flx0_clk>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xf8034000 0x800>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flx1: flexcom@f8038000 {
|
|
compatible = "atmel,sama5d2-flexcom";
|
|
reg = <0xf8038000 0x200>;
|
|
clocks = <&flx1_clk>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xf8038000 0x800>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rstc@f8048000 {
|
|
compatible = "atmel,sama5d3-rstc";
|
|
reg = <0xf8048000 0x10>;
|
|
clocks = <&clk32k>;
|
|
};
|
|
|
|
pit: timer@f8048030 {
|
|
compatible = "atmel,at91sam9260-pit";
|
|
reg = <0xf8048030 0x10>;
|
|
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
clocks = <&h32ck>;
|
|
};
|
|
|
|
sckc@f8048050 {
|
|
compatible = "atmel,at91sam9x5-sckc";
|
|
reg = <0xf8048050 0x4>;
|
|
|
|
slow_rc_osc: slow_rc_osc {
|
|
compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32768>;
|
|
clock-accuracy = <250000000>;
|
|
atmel,startup-time-usec = <75>;
|
|
};
|
|
|
|
slow_osc: slow_osc {
|
|
compatible = "atmel,at91sam9x5-clk-slow-osc";
|
|
#clock-cells = <0>;
|
|
clocks = <&slow_xtal>;
|
|
atmel,startup-time-usec = <1200000>;
|
|
};
|
|
|
|
clk32k: slowck {
|
|
compatible = "atmel,at91sam9x5-clk-slow";
|
|
#clock-cells = <0>;
|
|
clocks = <&slow_rc_osc &slow_osc>;
|
|
};
|
|
};
|
|
|
|
rtc@f80480b0 {
|
|
compatible = "atmel,at91rm9200-rtc";
|
|
reg = <0xf80480b0 0x30>;
|
|
interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
clocks = <&clk32k>;
|
|
};
|
|
|
|
spi1: spi@fc000000 {
|
|
compatible = "atmel,at91rm9200-spi";
|
|
reg = <0xfc000000 0x100>;
|
|
interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(8))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(9))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&spi1_clk>;
|
|
clock-names = "spi_clk";
|
|
atmel,fifo-size = <16>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@fc008000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xfc008000 0x100>;
|
|
interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
clocks = <&uart3_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@fc00c000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xfc00c000 0x100>;
|
|
interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
clocks = <&uart4_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
flx2: flexcom@fc010000 {
|
|
compatible = "atmel,sama5d2-flexcom";
|
|
reg = <0xfc010000 0x200>;
|
|
clocks = <&flx2_clk>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xfc010000 0x800>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flx3: flexcom@fc014000 {
|
|
compatible = "atmel,sama5d2-flexcom";
|
|
reg = <0xfc014000 0x200>;
|
|
clocks = <&flx3_clk>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xfc014000 0x800>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flx4: flexcom@fc018000 {
|
|
compatible = "atmel,sama5d2-flexcom";
|
|
reg = <0xfc018000 0x200>;
|
|
clocks = <&flx4_clk>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xfc018000 0x800>;
|
|
status = "disabled";
|
|
};
|
|
|
|
aic: interrupt-controller@fc020000 {
|
|
#interrupt-cells = <3>;
|
|
compatible = "atmel,sama5d2-aic";
|
|
interrupt-controller;
|
|
reg = <0xfc020000 0x200>;
|
|
atmel,external-irqs = <49>;
|
|
};
|
|
|
|
i2c1: i2c@fc028000 {
|
|
compatible = "atmel,sama5d2-i2c";
|
|
reg = <0xfc028000 0x100>;
|
|
interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(2))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(3))>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&twi1_clk>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pioA: pinctrl@fc038000 {
|
|
compatible = "atmel,sama5d2-pinctrl";
|
|
reg = <0xfc038000 0x600>;
|
|
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
|
|
<68 IRQ_TYPE_LEVEL_HIGH 7>,
|
|
<69 IRQ_TYPE_LEVEL_HIGH 7>,
|
|
<70 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
clocks = <&pioA_clk>;
|
|
};
|
|
|
|
tdes@fc044000 {
|
|
compatible = "atmel,at91sam9g46-tdes";
|
|
reg = <0xfc044000 0x100>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(28))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(29))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&tdes_clk>;
|
|
clock-names = "tdes_clk";
|
|
status = "okay";
|
|
};
|
|
};
|
|
};
|
|
};
|