forked from Minki/linux
697d3899dc
This provides the low-level support for MMIO emulation in Book3S HV guests. When the guest tries to map a page which is not covered by any memslot, that page is taken to be an MMIO emulation page. Instead of inserting a valid HPTE, we insert an HPTE that has the valid bit clear but another hypervisor software-use bit set, which we call HPTE_V_ABSENT, to indicate that this is an absent page. An absent page is treated much like a valid page as far as guest hcalls (H_ENTER, H_REMOVE, H_READ etc.) are concerned, except of course that an absent HPTE doesn't need to be invalidated with tlbie since it was never valid as far as the hardware is concerned. When the guest accesses a page for which there is an absent HPTE, it will take a hypervisor data storage interrupt (HDSI) since we now set the VPM1 bit in the LPCR. Our HDSI handler for HPTE-not-present faults looks up the hash table and if it finds an absent HPTE mapping the requested virtual address, will switch to kernel mode and handle the fault in kvmppc_book3s_hv_page_fault(), which at present just calls kvmppc_hv_emulate_mmio() to set up the MMIO emulation. This is based on an earlier patch by Benjamin Herrenschmidt, but since heavily reworked. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Avi Kivity <avi@redhat.com>
680 lines
18 KiB
C
680 lines
18 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* Copyright 2010-2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
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*/
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#include <linux/types.h>
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#include <linux/string.h>
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <linux/hugetlb.h>
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#include <linux/module.h>
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#include <asm/tlbflush.h>
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#include <asm/kvm_ppc.h>
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#include <asm/kvm_book3s.h>
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#include <asm/mmu-hash64.h>
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#include <asm/hvcall.h>
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#include <asm/synch.h>
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#include <asm/ppc-opcode.h>
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/*
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* Since this file is built in even if KVM is a module, we need
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* a local copy of this function for the case where kvm_main.c is
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* modular.
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*/
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static struct kvm_memory_slot *builtin_gfn_to_memslot(struct kvm *kvm,
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gfn_t gfn)
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{
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struct kvm_memslots *slots;
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struct kvm_memory_slot *memslot;
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slots = kvm_memslots(kvm);
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kvm_for_each_memslot(memslot, slots)
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if (gfn >= memslot->base_gfn &&
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gfn < memslot->base_gfn + memslot->npages)
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return memslot;
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return NULL;
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}
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/* Translate address of a vmalloc'd thing to a linear map address */
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static void *real_vmalloc_addr(void *x)
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{
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unsigned long addr = (unsigned long) x;
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pte_t *p;
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p = find_linux_pte(swapper_pg_dir, addr);
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if (!p || !pte_present(*p))
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return NULL;
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/* assume we don't have huge pages in vmalloc space... */
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addr = (pte_pfn(*p) << PAGE_SHIFT) | (addr & ~PAGE_MASK);
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return __va(addr);
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}
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/*
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* Add this HPTE into the chain for the real page.
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* Must be called with the chain locked; it unlocks the chain.
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*/
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static void kvmppc_add_revmap_chain(struct kvm *kvm, struct revmap_entry *rev,
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unsigned long *rmap, long pte_index, int realmode)
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{
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struct revmap_entry *head, *tail;
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unsigned long i;
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if (*rmap & KVMPPC_RMAP_PRESENT) {
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i = *rmap & KVMPPC_RMAP_INDEX;
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head = &kvm->arch.revmap[i];
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if (realmode)
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head = real_vmalloc_addr(head);
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tail = &kvm->arch.revmap[head->back];
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if (realmode)
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tail = real_vmalloc_addr(tail);
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rev->forw = i;
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rev->back = head->back;
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tail->forw = pte_index;
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head->back = pte_index;
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} else {
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rev->forw = rev->back = pte_index;
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i = pte_index;
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}
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smp_wmb();
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*rmap = i | KVMPPC_RMAP_REFERENCED | KVMPPC_RMAP_PRESENT; /* unlock */
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}
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/* Remove this HPTE from the chain for a real page */
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static void remove_revmap_chain(struct kvm *kvm, long pte_index,
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unsigned long hpte_v)
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{
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struct revmap_entry *rev, *next, *prev;
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unsigned long gfn, ptel, head;
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struct kvm_memory_slot *memslot;
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unsigned long *rmap;
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rev = real_vmalloc_addr(&kvm->arch.revmap[pte_index]);
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ptel = rev->guest_rpte;
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gfn = hpte_rpn(ptel, hpte_page_size(hpte_v, ptel));
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memslot = builtin_gfn_to_memslot(kvm, gfn);
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if (!memslot || (memslot->flags & KVM_MEMSLOT_INVALID))
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return;
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rmap = real_vmalloc_addr(&memslot->rmap[gfn - memslot->base_gfn]);
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lock_rmap(rmap);
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head = *rmap & KVMPPC_RMAP_INDEX;
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next = real_vmalloc_addr(&kvm->arch.revmap[rev->forw]);
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prev = real_vmalloc_addr(&kvm->arch.revmap[rev->back]);
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next->back = rev->back;
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prev->forw = rev->forw;
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if (head == pte_index) {
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head = rev->forw;
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if (head == pte_index)
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*rmap &= ~(KVMPPC_RMAP_PRESENT | KVMPPC_RMAP_INDEX);
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else
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*rmap = (*rmap & ~KVMPPC_RMAP_INDEX) | head;
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}
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unlock_rmap(rmap);
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}
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long kvmppc_h_enter(struct kvm_vcpu *vcpu, unsigned long flags,
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long pte_index, unsigned long pteh, unsigned long ptel)
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{
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struct kvm *kvm = vcpu->kvm;
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unsigned long i, pa, gpa, gfn, psize;
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unsigned long slot_fn;
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unsigned long *hpte;
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struct revmap_entry *rev;
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unsigned long g_ptel = ptel;
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struct kvm_memory_slot *memslot;
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unsigned long *physp, pte_size;
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unsigned long is_io;
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unsigned long *rmap;
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bool realmode = vcpu->arch.vcore->vcore_state == VCORE_RUNNING;
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psize = hpte_page_size(pteh, ptel);
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if (!psize)
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return H_PARAMETER;
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pteh &= ~(HPTE_V_HVLOCK | HPTE_V_ABSENT | HPTE_V_VALID);
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/* Find the memslot (if any) for this address */
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gpa = (ptel & HPTE_R_RPN) & ~(psize - 1);
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gfn = gpa >> PAGE_SHIFT;
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memslot = builtin_gfn_to_memslot(kvm, gfn);
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pa = 0;
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rmap = NULL;
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if (!(memslot && !(memslot->flags & KVM_MEMSLOT_INVALID))) {
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/* PPC970 can't do emulated MMIO */
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if (!cpu_has_feature(CPU_FTR_ARCH_206))
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return H_PARAMETER;
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/* Emulated MMIO - mark this with key=31 */
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pteh |= HPTE_V_ABSENT;
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ptel |= HPTE_R_KEY_HI | HPTE_R_KEY_LO;
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goto do_insert;
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}
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/* Check if the requested page fits entirely in the memslot. */
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if (!slot_is_aligned(memslot, psize))
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return H_PARAMETER;
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slot_fn = gfn - memslot->base_gfn;
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rmap = &memslot->rmap[slot_fn];
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physp = kvm->arch.slot_phys[memslot->id];
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if (!physp)
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return H_PARAMETER;
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physp += slot_fn;
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if (realmode)
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physp = real_vmalloc_addr(physp);
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pa = *physp;
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if (!pa)
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return H_TOO_HARD;
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is_io = pa & (HPTE_R_I | HPTE_R_W);
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pte_size = PAGE_SIZE << (pa & KVMPPC_PAGE_ORDER_MASK);
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pa &= PAGE_MASK;
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if (pte_size < psize)
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return H_PARAMETER;
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if (pa && pte_size > psize)
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pa |= gpa & (pte_size - 1);
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ptel &= ~(HPTE_R_PP0 - psize);
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ptel |= pa;
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pteh |= HPTE_V_VALID;
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/* Check WIMG */
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if (!hpte_cache_flags_ok(ptel, is_io)) {
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if (is_io)
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return H_PARAMETER;
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/*
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* Allow guest to map emulated device memory as
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* uncacheable, but actually make it cacheable.
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*/
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ptel &= ~(HPTE_R_W|HPTE_R_I|HPTE_R_G);
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ptel |= HPTE_R_M;
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}
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do_insert:
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if (pte_index >= HPT_NPTE)
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return H_PARAMETER;
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if (likely((flags & H_EXACT) == 0)) {
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pte_index &= ~7UL;
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hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
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for (i = 0; i < 8; ++i) {
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if ((*hpte & HPTE_V_VALID) == 0 &&
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try_lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID |
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HPTE_V_ABSENT))
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break;
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hpte += 2;
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}
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if (i == 8) {
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/*
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* Since try_lock_hpte doesn't retry (not even stdcx.
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* failures), it could be that there is a free slot
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* but we transiently failed to lock it. Try again,
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* actually locking each slot and checking it.
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*/
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hpte -= 16;
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for (i = 0; i < 8; ++i) {
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while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
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cpu_relax();
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if (!(*hpte & (HPTE_V_VALID | HPTE_V_ABSENT)))
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break;
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*hpte &= ~HPTE_V_HVLOCK;
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hpte += 2;
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}
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if (i == 8)
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return H_PTEG_FULL;
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}
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pte_index += i;
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} else {
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hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
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if (!try_lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID |
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HPTE_V_ABSENT)) {
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/* Lock the slot and check again */
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while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
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cpu_relax();
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if (*hpte & (HPTE_V_VALID | HPTE_V_ABSENT)) {
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*hpte &= ~HPTE_V_HVLOCK;
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return H_PTEG_FULL;
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}
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}
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}
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/* Save away the guest's idea of the second HPTE dword */
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rev = &kvm->arch.revmap[pte_index];
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if (realmode)
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rev = real_vmalloc_addr(rev);
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if (rev)
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rev->guest_rpte = g_ptel;
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/* Link HPTE into reverse-map chain */
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if (pteh & HPTE_V_VALID) {
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if (realmode)
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rmap = real_vmalloc_addr(rmap);
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lock_rmap(rmap);
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kvmppc_add_revmap_chain(kvm, rev, rmap, pte_index, realmode);
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}
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hpte[1] = ptel;
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/* Write the first HPTE dword, unlocking the HPTE and making it valid */
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eieio();
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hpte[0] = pteh;
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asm volatile("ptesync" : : : "memory");
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vcpu->arch.gpr[4] = pte_index;
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return H_SUCCESS;
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}
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EXPORT_SYMBOL_GPL(kvmppc_h_enter);
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#define LOCK_TOKEN (*(u32 *)(&get_paca()->lock_token))
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static inline int try_lock_tlbie(unsigned int *lock)
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{
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unsigned int tmp, old;
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unsigned int token = LOCK_TOKEN;
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asm volatile("1:lwarx %1,0,%2\n"
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" cmpwi cr0,%1,0\n"
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" bne 2f\n"
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" stwcx. %3,0,%2\n"
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" bne- 1b\n"
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" isync\n"
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"2:"
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: "=&r" (tmp), "=&r" (old)
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: "r" (lock), "r" (token)
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: "cc", "memory");
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return old == 0;
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}
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long kvmppc_h_remove(struct kvm_vcpu *vcpu, unsigned long flags,
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unsigned long pte_index, unsigned long avpn,
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unsigned long va)
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{
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struct kvm *kvm = vcpu->kvm;
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unsigned long *hpte;
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unsigned long v, r, rb;
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if (pte_index >= HPT_NPTE)
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return H_PARAMETER;
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hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
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while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
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cpu_relax();
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if ((hpte[0] & (HPTE_V_ABSENT | HPTE_V_VALID)) == 0 ||
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((flags & H_AVPN) && (hpte[0] & ~0x7fUL) != avpn) ||
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((flags & H_ANDCOND) && (hpte[0] & avpn) != 0)) {
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hpte[0] &= ~HPTE_V_HVLOCK;
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return H_NOT_FOUND;
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}
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if (atomic_read(&kvm->online_vcpus) == 1)
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flags |= H_LOCAL;
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vcpu->arch.gpr[4] = v = hpte[0] & ~HPTE_V_HVLOCK;
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vcpu->arch.gpr[5] = r = hpte[1];
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rb = compute_tlbie_rb(v, r, pte_index);
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if (v & HPTE_V_VALID)
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remove_revmap_chain(kvm, pte_index, v);
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smp_wmb();
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hpte[0] = 0;
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if (!(v & HPTE_V_VALID))
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return H_SUCCESS;
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if (!(flags & H_LOCAL)) {
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while (!try_lock_tlbie(&kvm->arch.tlbie_lock))
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cpu_relax();
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asm volatile("ptesync" : : : "memory");
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asm volatile(PPC_TLBIE(%1,%0)"; eieio; tlbsync"
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: : "r" (rb), "r" (kvm->arch.lpid));
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asm volatile("ptesync" : : : "memory");
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kvm->arch.tlbie_lock = 0;
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} else {
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asm volatile("ptesync" : : : "memory");
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asm volatile("tlbiel %0" : : "r" (rb));
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asm volatile("ptesync" : : : "memory");
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}
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return H_SUCCESS;
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}
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long kvmppc_h_bulk_remove(struct kvm_vcpu *vcpu)
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{
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struct kvm *kvm = vcpu->kvm;
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unsigned long *args = &vcpu->arch.gpr[4];
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unsigned long *hp, tlbrb[4];
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long int i, found;
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long int n_inval = 0;
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unsigned long flags, req, pte_index;
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long int local = 0;
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long int ret = H_SUCCESS;
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if (atomic_read(&kvm->online_vcpus) == 1)
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local = 1;
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for (i = 0; i < 4; ++i) {
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pte_index = args[i * 2];
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flags = pte_index >> 56;
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pte_index &= ((1ul << 56) - 1);
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req = flags >> 6;
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flags &= 3;
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if (req == 3)
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break;
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if (req != 1 || flags == 3 ||
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pte_index >= HPT_NPTE) {
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/* parameter error */
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args[i * 2] = ((0xa0 | flags) << 56) + pte_index;
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ret = H_PARAMETER;
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break;
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}
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hp = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
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while (!try_lock_hpte(hp, HPTE_V_HVLOCK))
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cpu_relax();
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found = 0;
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if (hp[0] & (HPTE_V_ABSENT | HPTE_V_VALID)) {
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switch (flags & 3) {
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case 0: /* absolute */
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found = 1;
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break;
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case 1: /* andcond */
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if (!(hp[0] & args[i * 2 + 1]))
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found = 1;
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break;
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case 2: /* AVPN */
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if ((hp[0] & ~0x7fUL) == args[i * 2 + 1])
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found = 1;
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break;
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}
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}
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if (!found) {
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hp[0] &= ~HPTE_V_HVLOCK;
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args[i * 2] = ((0x90 | flags) << 56) + pte_index;
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continue;
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}
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/* insert R and C bits from PTE */
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flags |= (hp[1] >> 5) & 0x0c;
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args[i * 2] = ((0x80 | flags) << 56) + pte_index;
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if (hp[0] & HPTE_V_VALID) {
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tlbrb[n_inval++] = compute_tlbie_rb(hp[0], hp[1], pte_index);
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remove_revmap_chain(kvm, pte_index, hp[0]);
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}
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smp_wmb();
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hp[0] = 0;
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}
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if (n_inval == 0)
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return ret;
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if (!local) {
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while(!try_lock_tlbie(&kvm->arch.tlbie_lock))
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cpu_relax();
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asm volatile("ptesync" : : : "memory");
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for (i = 0; i < n_inval; ++i)
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asm volatile(PPC_TLBIE(%1,%0)
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: : "r" (tlbrb[i]), "r" (kvm->arch.lpid));
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asm volatile("eieio; tlbsync; ptesync" : : : "memory");
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kvm->arch.tlbie_lock = 0;
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} else {
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asm volatile("ptesync" : : : "memory");
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for (i = 0; i < n_inval; ++i)
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asm volatile("tlbiel %0" : : "r" (tlbrb[i]));
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asm volatile("ptesync" : : : "memory");
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}
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return ret;
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}
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long kvmppc_h_protect(struct kvm_vcpu *vcpu, unsigned long flags,
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unsigned long pte_index, unsigned long avpn,
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unsigned long va)
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{
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struct kvm *kvm = vcpu->kvm;
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unsigned long *hpte;
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struct revmap_entry *rev;
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unsigned long v, r, rb, mask, bits;
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if (pte_index >= HPT_NPTE)
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return H_PARAMETER;
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hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
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while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
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cpu_relax();
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if ((hpte[0] & (HPTE_V_ABSENT | HPTE_V_VALID)) == 0 ||
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((flags & H_AVPN) && (hpte[0] & ~0x7fUL) != avpn)) {
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hpte[0] &= ~HPTE_V_HVLOCK;
|
|
return H_NOT_FOUND;
|
|
}
|
|
|
|
if (atomic_read(&kvm->online_vcpus) == 1)
|
|
flags |= H_LOCAL;
|
|
v = hpte[0];
|
|
bits = (flags << 55) & HPTE_R_PP0;
|
|
bits |= (flags << 48) & HPTE_R_KEY_HI;
|
|
bits |= flags & (HPTE_R_PP | HPTE_R_N | HPTE_R_KEY_LO);
|
|
|
|
/* Update guest view of 2nd HPTE dword */
|
|
mask = HPTE_R_PP0 | HPTE_R_PP | HPTE_R_N |
|
|
HPTE_R_KEY_HI | HPTE_R_KEY_LO;
|
|
rev = real_vmalloc_addr(&kvm->arch.revmap[pte_index]);
|
|
if (rev) {
|
|
r = (rev->guest_rpte & ~mask) | bits;
|
|
rev->guest_rpte = r;
|
|
}
|
|
r = (hpte[1] & ~mask) | bits;
|
|
|
|
/* Update HPTE */
|
|
if (v & HPTE_V_VALID) {
|
|
rb = compute_tlbie_rb(v, r, pte_index);
|
|
hpte[0] = v & ~HPTE_V_VALID;
|
|
if (!(flags & H_LOCAL)) {
|
|
while(!try_lock_tlbie(&kvm->arch.tlbie_lock))
|
|
cpu_relax();
|
|
asm volatile("ptesync" : : : "memory");
|
|
asm volatile(PPC_TLBIE(%1,%0)"; eieio; tlbsync"
|
|
: : "r" (rb), "r" (kvm->arch.lpid));
|
|
asm volatile("ptesync" : : : "memory");
|
|
kvm->arch.tlbie_lock = 0;
|
|
} else {
|
|
asm volatile("ptesync" : : : "memory");
|
|
asm volatile("tlbiel %0" : : "r" (rb));
|
|
asm volatile("ptesync" : : : "memory");
|
|
}
|
|
}
|
|
hpte[1] = r;
|
|
eieio();
|
|
hpte[0] = v & ~HPTE_V_HVLOCK;
|
|
asm volatile("ptesync" : : : "memory");
|
|
return H_SUCCESS;
|
|
}
|
|
|
|
long kvmppc_h_read(struct kvm_vcpu *vcpu, unsigned long flags,
|
|
unsigned long pte_index)
|
|
{
|
|
struct kvm *kvm = vcpu->kvm;
|
|
unsigned long *hpte, v, r;
|
|
int i, n = 1;
|
|
struct revmap_entry *rev = NULL;
|
|
|
|
if (pte_index >= HPT_NPTE)
|
|
return H_PARAMETER;
|
|
if (flags & H_READ_4) {
|
|
pte_index &= ~3;
|
|
n = 4;
|
|
}
|
|
if (flags & H_R_XLATE)
|
|
rev = real_vmalloc_addr(&kvm->arch.revmap[pte_index]);
|
|
for (i = 0; i < n; ++i, ++pte_index) {
|
|
hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
|
|
v = hpte[0] & ~HPTE_V_HVLOCK;
|
|
r = hpte[1];
|
|
if (v & HPTE_V_ABSENT) {
|
|
v &= ~HPTE_V_ABSENT;
|
|
v |= HPTE_V_VALID;
|
|
}
|
|
if (v & HPTE_V_VALID) {
|
|
if (rev)
|
|
r = rev[i].guest_rpte;
|
|
else
|
|
r = hpte[1] | HPTE_R_RPN;
|
|
}
|
|
vcpu->arch.gpr[4 + i * 2] = v;
|
|
vcpu->arch.gpr[5 + i * 2] = r;
|
|
}
|
|
return H_SUCCESS;
|
|
}
|
|
|
|
static int slb_base_page_shift[4] = {
|
|
24, /* 16M */
|
|
16, /* 64k */
|
|
34, /* 16G */
|
|
20, /* 1M, unsupported */
|
|
};
|
|
|
|
long kvmppc_hv_find_lock_hpte(struct kvm *kvm, gva_t eaddr, unsigned long slb_v,
|
|
unsigned long valid)
|
|
{
|
|
unsigned int i;
|
|
unsigned int pshift;
|
|
unsigned long somask;
|
|
unsigned long vsid, hash;
|
|
unsigned long avpn;
|
|
unsigned long *hpte;
|
|
unsigned long mask, val;
|
|
unsigned long v, r;
|
|
|
|
/* Get page shift, work out hash and AVPN etc. */
|
|
mask = SLB_VSID_B | HPTE_V_AVPN | HPTE_V_SECONDARY;
|
|
val = 0;
|
|
pshift = 12;
|
|
if (slb_v & SLB_VSID_L) {
|
|
mask |= HPTE_V_LARGE;
|
|
val |= HPTE_V_LARGE;
|
|
pshift = slb_base_page_shift[(slb_v & SLB_VSID_LP) >> 4];
|
|
}
|
|
if (slb_v & SLB_VSID_B_1T) {
|
|
somask = (1UL << 40) - 1;
|
|
vsid = (slb_v & ~SLB_VSID_B) >> SLB_VSID_SHIFT_1T;
|
|
vsid ^= vsid << 25;
|
|
} else {
|
|
somask = (1UL << 28) - 1;
|
|
vsid = (slb_v & ~SLB_VSID_B) >> SLB_VSID_SHIFT;
|
|
}
|
|
hash = (vsid ^ ((eaddr & somask) >> pshift)) & HPT_HASH_MASK;
|
|
avpn = slb_v & ~(somask >> 16); /* also includes B */
|
|
avpn |= (eaddr & somask) >> 16;
|
|
|
|
if (pshift >= 24)
|
|
avpn &= ~((1UL << (pshift - 16)) - 1);
|
|
else
|
|
avpn &= ~0x7fUL;
|
|
val |= avpn;
|
|
|
|
for (;;) {
|
|
hpte = (unsigned long *)(kvm->arch.hpt_virt + (hash << 7));
|
|
|
|
for (i = 0; i < 16; i += 2) {
|
|
/* Read the PTE racily */
|
|
v = hpte[i] & ~HPTE_V_HVLOCK;
|
|
|
|
/* Check valid/absent, hash, segment size and AVPN */
|
|
if (!(v & valid) || (v & mask) != val)
|
|
continue;
|
|
|
|
/* Lock the PTE and read it under the lock */
|
|
while (!try_lock_hpte(&hpte[i], HPTE_V_HVLOCK))
|
|
cpu_relax();
|
|
v = hpte[i] & ~HPTE_V_HVLOCK;
|
|
r = hpte[i+1];
|
|
|
|
/*
|
|
* Check the HPTE again, including large page size
|
|
* Since we don't currently allow any MPSS (mixed
|
|
* page-size segment) page sizes, it is sufficient
|
|
* to check against the actual page size.
|
|
*/
|
|
if ((v & valid) && (v & mask) == val &&
|
|
hpte_page_size(v, r) == (1ul << pshift))
|
|
/* Return with the HPTE still locked */
|
|
return (hash << 3) + (i >> 1);
|
|
|
|
/* Unlock and move on */
|
|
hpte[i] = v;
|
|
}
|
|
|
|
if (val & HPTE_V_SECONDARY)
|
|
break;
|
|
val |= HPTE_V_SECONDARY;
|
|
hash = hash ^ HPT_HASH_MASK;
|
|
}
|
|
return -1;
|
|
}
|
|
EXPORT_SYMBOL(kvmppc_hv_find_lock_hpte);
|
|
|
|
/*
|
|
* Called in real mode to check whether an HPTE not found fault
|
|
* is due to accessing an emulated MMIO page.
|
|
* Returns a possibly modified status (DSISR) value if not
|
|
* (i.e. pass the interrupt to the guest),
|
|
* -1 to pass the fault up to host kernel mode code, -2 to do that
|
|
* and also load the instruction word,
|
|
* or 0 if we should make the guest retry the access.
|
|
*/
|
|
long kvmppc_hpte_hv_fault(struct kvm_vcpu *vcpu, unsigned long addr,
|
|
unsigned long slb_v, unsigned int status)
|
|
{
|
|
struct kvm *kvm = vcpu->kvm;
|
|
long int index;
|
|
unsigned long v, r, gr;
|
|
unsigned long *hpte;
|
|
unsigned long valid;
|
|
struct revmap_entry *rev;
|
|
unsigned long pp, key;
|
|
|
|
valid = HPTE_V_VALID | HPTE_V_ABSENT;
|
|
index = kvmppc_hv_find_lock_hpte(kvm, addr, slb_v, valid);
|
|
if (index < 0)
|
|
return status; /* there really was no HPTE */
|
|
|
|
hpte = (unsigned long *)(kvm->arch.hpt_virt + (index << 4));
|
|
v = hpte[0] & ~HPTE_V_HVLOCK;
|
|
r = hpte[1];
|
|
rev = real_vmalloc_addr(&kvm->arch.revmap[index]);
|
|
gr = rev->guest_rpte;
|
|
|
|
/* Unlock the HPTE */
|
|
asm volatile("lwsync" : : : "memory");
|
|
hpte[0] = v;
|
|
|
|
/* If the HPTE is valid by now, retry the instruction */
|
|
if (v & HPTE_V_VALID)
|
|
return 0;
|
|
|
|
/* Check access permissions to the page */
|
|
pp = gr & (HPTE_R_PP0 | HPTE_R_PP);
|
|
key = (vcpu->arch.shregs.msr & MSR_PR) ? SLB_VSID_KP : SLB_VSID_KS;
|
|
if (status & DSISR_ISSTORE) {
|
|
/* check write permission */
|
|
if (!hpte_write_permission(pp, slb_v & key))
|
|
goto protfault;
|
|
} else {
|
|
if (!hpte_read_permission(pp, slb_v & key))
|
|
goto protfault;
|
|
}
|
|
|
|
/* Check storage key, if applicable */
|
|
if (vcpu->arch.shregs.msr & MSR_DR) {
|
|
unsigned int perm = hpte_get_skey_perm(gr, vcpu->arch.amr);
|
|
if (status & DSISR_ISSTORE)
|
|
perm >>= 1;
|
|
if (perm & 1)
|
|
return (status & ~DSISR_NOHPTE) | DSISR_KEYFAULT;
|
|
}
|
|
|
|
/* Save HPTE info for virtual-mode handler */
|
|
vcpu->arch.pgfault_addr = addr;
|
|
vcpu->arch.pgfault_index = index;
|
|
vcpu->arch.pgfault_hpte[0] = v;
|
|
vcpu->arch.pgfault_hpte[1] = r;
|
|
|
|
if (vcpu->arch.shregs.msr & MSR_IR)
|
|
return -2; /* MMIO emulation - load instr word */
|
|
|
|
return -1; /* send fault up to host kernel mode */
|
|
|
|
protfault:
|
|
return (status & ~DSISR_NOHPTE) | DSISR_PROTFAULT;
|
|
}
|