forked from Minki/linux
b381f783ba
Only compile-tested - I don't have the hardware. >From code inspection, octeon_pci_write_core_mem() appears to be safe wrt unaligned source. In any case, u8 fbuf[] was not guaranteed to be aligned anyway. Signed-off-by: Denys Vlasenko <dvlasenk@redhat.com> CC: Felix Manlunas <felix.manlunas@cavium.com> CC: Prasad Kanneganti <prasad.kanneganti@cavium.com> CC: Derek Chickles <derek.chickles@cavium.com> CC: David Miller <davem@davemloft.net> CC: netdev@vger.kernel.org CC: linux-kernel@vger.kernel.org Acked-by: Felix Manlunas <felix.manlunas@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
73 lines
2.2 KiB
C
73 lines
2.2 KiB
C
/**********************************************************************
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* Author: Cavium, Inc.
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*
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* Contact: support@cavium.com
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* Please include "LiquidIO" in the subject.
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*
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* Copyright (c) 2003-2016 Cavium, Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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**********************************************************************/
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/*! \file octeon_mem_ops.h
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* \brief Host Driver: Routines used to read/write Octeon memory.
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*/
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#ifndef __OCTEON_MEM_OPS_H__
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#define __OCTEON_MEM_OPS_H__
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/** Read a 64-bit value from a BAR1 mapped core memory address.
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* @param oct - pointer to the octeon device.
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* @param core_addr - the address to read from.
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*
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* The range_idx gives the BAR1 index register for the range of address
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* in which core_addr is mapped.
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*
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* @return 64-bit value read from Core memory
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*/
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u64 octeon_read_device_mem64(struct octeon_device *oct, u64 core_addr);
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/** Read a 32-bit value from a BAR1 mapped core memory address.
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* @param oct - pointer to the octeon device.
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* @param core_addr - the address to read from.
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*
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* @return 32-bit value read from Core memory
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*/
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u32 octeon_read_device_mem32(struct octeon_device *oct, u64 core_addr);
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/** Write a 32-bit value to a BAR1 mapped core memory address.
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* @param oct - pointer to the octeon device.
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* @param core_addr - the address to write to.
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* @param val - 32-bit value to write.
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*/
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void
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octeon_write_device_mem32(struct octeon_device *oct,
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u64 core_addr,
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u32 val);
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/** Read multiple bytes from Octeon memory.
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*/
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void
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octeon_pci_read_core_mem(struct octeon_device *oct,
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u64 coreaddr,
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u8 *buf,
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u32 len);
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/** Write multiple bytes into Octeon memory.
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*/
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void
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octeon_pci_write_core_mem(struct octeon_device *oct,
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u64 coreaddr,
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const u8 *buf,
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u32 len);
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#endif
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