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Some boards [1] leave the PHYs at an invalid state during system power-up or reset thus causing unreliability issues with the PHY which manifests as PHY not being detected or link not functional. To fix this, these PHYs need to be RESET via a GPIO connected to the PHY's RESET pin. Some boards have a single GPIO controlling the PHY RESET pin of all PHYs on the bus whereas some others have separate GPIOs controlling individual PHY RESETs. In both cases, the RESET de-assertion cannot be done in the PHY driver as the PHY will not probe till its reset is de-asserted. So do the RESET de-assertion in the MDIO bus driver. [1] - am572x-idk, am571x-idk, a437x-idk Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
34 lines
903 B
Plaintext
34 lines
903 B
Plaintext
Common MDIO bus properties.
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These are generic properties that can apply to any MDIO bus.
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Optional properties:
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- reset-gpios: List of one or more GPIOs that control the RESET lines
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of the PHYs on that MDIO bus.
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- reset-delay-us: RESET pulse width in microseconds as per PHY datasheet.
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A list of child nodes, one per device on the bus is expected. These
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should follow the generic phy.txt, or a device specific binding document.
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Example :
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This example shows these optional properties, plus other properties
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required for the TI Davinci MDIO driver.
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davinci_mdio: ethernet@0x5c030000 {
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compatible = "ti,davinci_mdio";
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reg = <0x5c030000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
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reset-delay-us = <2>; /* PHY datasheet states 1us min */
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ethphy0: ethernet-phy@1 {
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reg = <1>;
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};
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ethphy1: ethernet-phy@3 {
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reg = <3>;
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};
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};
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