linux/drivers/gpu
Chen-Yu Tsai cc67ae90be drm/sun4i: hdmi: Allow using second PLL as TMDS clk parent
On SoCs with two display pipelines, it is possible that the two
pipelines are active at the same time, with potentially incompatible
dot clocks.

Let the HDMI encoder's TMDS clock go through all of its parents when
calculating possible clock rates. This allows usage of the second video
PLL as its parent.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171010032008.682-6-wens@csie.org
2017-10-11 09:53:13 +02:00
..
drm drm/sun4i: hdmi: Allow using second PLL as TMDS clk parent 2017-10-11 09:53:13 +02:00
host1x drm/tegra: Changes for v4.14-rc1 2017-08-21 17:37:33 +10:00
ipu-v3 main drm pull request for 4.14 merge window 2017-09-03 17:02:26 -07:00
vga sched/wait: Rename wait_queue_t => wait_queue_entry_t 2017-06-20 12:18:27 +02:00
Makefile