forked from Minki/linux
d42986b6c6
Currently the framebuffer content is displayed with incorrect offsets in both the vertical and horizontal directions. The fbdev version of the driver does not show this problem. Breno Lima dumped the eLCDIF controller registers on both the drm and fbdev drivers and noticed that the VDCTRL3 register is configured incorrectly in the drm driver. The fbdev driver calculates the vertical and horizontal wait counts of the VDCTRL3 register by doing: back porch + sync length. Looking at the horizontal and vertical timing diagram from include/drm/drm_modes.h this value corresponds to: crtc_[hv]total - crtc_[hv]sync_start So fix the VDCTRL3 register setting accordingly so that the eLCDIF controller can properly show the framebuffer content in the correct position. Reported-by: Breno Lima <breno.lima@nxp.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Breno Lima <breno.lima@nxp.com> Tested-by: Marek Vasut <marex@denx.de> Signed-off-by: Dave Airlie <airlied@redhat.com>
279 lines
8.1 KiB
C
279 lines
8.1 KiB
C
/*
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* Copyright (C) 2016 Marek Vasut <marex@denx.de>
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*
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* This code is based on drivers/video/fbdev/mxsfb.c :
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* Copyright (C) 2010 Juergen Beisert, Pengutronix
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* Copyright (C) 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright (C) 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <drm/drmP.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_fb_helper.h>
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#include <drm/drm_fb_cma_helper.h>
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#include <drm/drm_gem_cma_helper.h>
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#include <drm/drm_of.h>
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#include <drm/drm_plane_helper.h>
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#include <drm/drm_simple_kms_helper.h>
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#include <linux/clk.h>
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#include <linux/iopoll.h>
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#include <linux/of_graph.h>
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#include <linux/platform_data/simplefb.h>
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#include <video/videomode.h>
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#include "mxsfb_drv.h"
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#include "mxsfb_regs.h"
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static u32 set_hsync_pulse_width(struct mxsfb_drm_private *mxsfb, u32 val)
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{
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return (val & mxsfb->devdata->hs_wdth_mask) <<
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mxsfb->devdata->hs_wdth_shift;
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}
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/* Setup the MXSFB registers for decoding the pixels out of the framebuffer */
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static int mxsfb_set_pixel_fmt(struct mxsfb_drm_private *mxsfb)
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{
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struct drm_crtc *crtc = &mxsfb->pipe.crtc;
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struct drm_device *drm = crtc->dev;
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const u32 format = crtc->primary->state->fb->format->format;
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u32 ctrl, ctrl1;
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ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER;
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/*
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* WARNING: The bus width, CTRL_SET_BUS_WIDTH(), is configured to
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* match the selected mode here. This differs from the original
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* MXSFB driver, which had the option to configure the bus width
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* to arbitrary value. This limitation should not pose an issue.
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*/
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/* CTRL1 contains IRQ config and status bits, preserve those. */
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ctrl1 = readl(mxsfb->base + LCDC_CTRL1);
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ctrl1 &= CTRL1_CUR_FRAME_DONE_IRQ_EN | CTRL1_CUR_FRAME_DONE_IRQ;
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switch (format) {
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case DRM_FORMAT_RGB565:
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dev_dbg(drm->dev, "Setting up RGB565 mode\n");
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ctrl |= CTRL_SET_WORD_LENGTH(0);
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ctrl1 |= CTRL1_SET_BYTE_PACKAGING(0xf);
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break;
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case DRM_FORMAT_XRGB8888:
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dev_dbg(drm->dev, "Setting up XRGB8888 mode\n");
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ctrl |= CTRL_SET_WORD_LENGTH(3);
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/* Do not use packed pixels = one pixel per word instead. */
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ctrl1 |= CTRL1_SET_BYTE_PACKAGING(0x7);
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break;
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default:
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dev_err(drm->dev, "Unhandled pixel format %08x\n", format);
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return -EINVAL;
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}
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writel(ctrl1, mxsfb->base + LCDC_CTRL1);
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writel(ctrl, mxsfb->base + LCDC_CTRL);
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return 0;
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}
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static void mxsfb_set_bus_fmt(struct mxsfb_drm_private *mxsfb)
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{
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struct drm_crtc *crtc = &mxsfb->pipe.crtc;
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struct drm_device *drm = crtc->dev;
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u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
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u32 reg;
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reg = readl(mxsfb->base + LCDC_CTRL);
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if (mxsfb->connector.display_info.num_bus_formats)
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bus_format = mxsfb->connector.display_info.bus_formats[0];
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reg &= ~CTRL_BUS_WIDTH_MASK;
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switch (bus_format) {
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case MEDIA_BUS_FMT_RGB565_1X16:
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reg |= CTRL_SET_BUS_WIDTH(STMLCDIF_16BIT);
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break;
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case MEDIA_BUS_FMT_RGB666_1X18:
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reg |= CTRL_SET_BUS_WIDTH(STMLCDIF_18BIT);
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break;
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case MEDIA_BUS_FMT_RGB888_1X24:
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reg |= CTRL_SET_BUS_WIDTH(STMLCDIF_24BIT);
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break;
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default:
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dev_err(drm->dev, "Unknown media bus format %d\n", bus_format);
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break;
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}
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writel(reg, mxsfb->base + LCDC_CTRL);
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}
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static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb)
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{
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u32 reg;
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if (mxsfb->clk_disp_axi)
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clk_prepare_enable(mxsfb->clk_disp_axi);
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clk_prepare_enable(mxsfb->clk);
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mxsfb_enable_axi_clk(mxsfb);
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/* If it was disabled, re-enable the mode again */
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writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_SET);
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/* Enable the SYNC signals first, then the DMA engine */
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reg = readl(mxsfb->base + LCDC_VDCTRL4);
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reg |= VDCTRL4_SYNC_SIGNALS_ON;
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writel(reg, mxsfb->base + LCDC_VDCTRL4);
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writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_SET);
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}
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static void mxsfb_disable_controller(struct mxsfb_drm_private *mxsfb)
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{
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u32 reg;
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/*
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* Even if we disable the controller here, it will still continue
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* until its FIFOs are running out of data
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*/
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writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_CLR);
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readl_poll_timeout(mxsfb->base + LCDC_CTRL, reg, !(reg & CTRL_RUN),
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0, 1000);
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reg = readl(mxsfb->base + LCDC_VDCTRL4);
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reg &= ~VDCTRL4_SYNC_SIGNALS_ON;
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writel(reg, mxsfb->base + LCDC_VDCTRL4);
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mxsfb_disable_axi_clk(mxsfb);
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clk_disable_unprepare(mxsfb->clk);
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if (mxsfb->clk_disp_axi)
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clk_disable_unprepare(mxsfb->clk_disp_axi);
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}
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static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb)
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{
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struct drm_display_mode *m = &mxsfb->pipe.crtc.state->adjusted_mode;
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const u32 bus_flags = mxsfb->connector.display_info.bus_flags;
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u32 vdctrl0, vsync_pulse_len, hsync_pulse_len;
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int err;
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/*
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* It seems, you can't re-program the controller if it is still
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* running. This may lead to shifted pictures (FIFO issue?), so
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* first stop the controller and drain its FIFOs.
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*/
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mxsfb_enable_axi_clk(mxsfb);
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/* Clear the FIFOs */
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writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_SET);
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err = mxsfb_set_pixel_fmt(mxsfb);
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if (err)
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return;
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clk_set_rate(mxsfb->clk, m->crtc_clock * 1000);
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writel(TRANSFER_COUNT_SET_VCOUNT(m->crtc_vdisplay) |
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TRANSFER_COUNT_SET_HCOUNT(m->crtc_hdisplay),
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mxsfb->base + mxsfb->devdata->transfer_count);
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vsync_pulse_len = m->crtc_vsync_end - m->crtc_vsync_start;
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vdctrl0 = VDCTRL0_ENABLE_PRESENT | /* Always in DOTCLOCK mode */
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VDCTRL0_VSYNC_PERIOD_UNIT |
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VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
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VDCTRL0_SET_VSYNC_PULSE_WIDTH(vsync_pulse_len);
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if (m->flags & DRM_MODE_FLAG_PHSYNC)
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vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH;
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if (m->flags & DRM_MODE_FLAG_PVSYNC)
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vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH;
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/* Make sure Data Enable is high active by default */
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if (!(bus_flags & DRM_BUS_FLAG_DE_LOW))
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vdctrl0 |= VDCTRL0_ENABLE_ACT_HIGH;
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/*
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* DRM_BUS_FLAG_PIXDATA_ defines are controller centric,
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* controllers VDCTRL0_DOTCLK is display centric.
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* Drive on positive edge -> display samples on falling edge
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* DRM_BUS_FLAG_PIXDATA_POSEDGE -> VDCTRL0_DOTCLK_ACT_FALLING
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*/
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if (bus_flags & DRM_BUS_FLAG_PIXDATA_POSEDGE)
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vdctrl0 |= VDCTRL0_DOTCLK_ACT_FALLING;
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writel(vdctrl0, mxsfb->base + LCDC_VDCTRL0);
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mxsfb_set_bus_fmt(mxsfb);
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/* Frame length in lines. */
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writel(m->crtc_vtotal, mxsfb->base + LCDC_VDCTRL1);
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/* Line length in units of clocks or pixels. */
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hsync_pulse_len = m->crtc_hsync_end - m->crtc_hsync_start;
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writel(set_hsync_pulse_width(mxsfb, hsync_pulse_len) |
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VDCTRL2_SET_HSYNC_PERIOD(m->crtc_htotal),
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mxsfb->base + LCDC_VDCTRL2);
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writel(SET_HOR_WAIT_CNT(m->crtc_htotal - m->crtc_hsync_start) |
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SET_VERT_WAIT_CNT(m->crtc_vtotal - m->crtc_vsync_start),
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mxsfb->base + LCDC_VDCTRL3);
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writel(SET_DOTCLK_H_VALID_DATA_CNT(m->hdisplay),
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mxsfb->base + LCDC_VDCTRL4);
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mxsfb_disable_axi_clk(mxsfb);
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}
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void mxsfb_crtc_enable(struct mxsfb_drm_private *mxsfb)
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{
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mxsfb_crtc_mode_set_nofb(mxsfb);
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mxsfb_enable_controller(mxsfb);
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}
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void mxsfb_crtc_disable(struct mxsfb_drm_private *mxsfb)
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{
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mxsfb_disable_controller(mxsfb);
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}
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void mxsfb_plane_atomic_update(struct mxsfb_drm_private *mxsfb,
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struct drm_plane_state *state)
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{
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struct drm_simple_display_pipe *pipe = &mxsfb->pipe;
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struct drm_crtc *crtc = &pipe->crtc;
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struct drm_framebuffer *fb = pipe->plane.state->fb;
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struct drm_pending_vblank_event *event;
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struct drm_gem_cma_object *gem;
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if (!crtc)
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return;
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spin_lock_irq(&crtc->dev->event_lock);
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event = crtc->state->event;
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if (event) {
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crtc->state->event = NULL;
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if (drm_crtc_vblank_get(crtc) == 0) {
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drm_crtc_arm_vblank_event(crtc, event);
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} else {
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drm_crtc_send_vblank_event(crtc, event);
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}
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}
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spin_unlock_irq(&crtc->dev->event_lock);
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if (!fb)
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return;
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gem = drm_fb_cma_get_gem_obj(fb, 0);
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mxsfb_enable_axi_clk(mxsfb);
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writel(gem->paddr, mxsfb->base + mxsfb->devdata->next_buf);
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mxsfb_disable_axi_clk(mxsfb);
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}
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