forked from Minki/linux
b14cbdfd46
The Ux500 PRCC (peripheral reset and clock controller) can also control reset of the IP blocks, not just clocks. As the PRCC is probed as a clock controller and we have other platforms implementing combined clock and reset controllers, follow this pattern and implement the PRCC rest controller as part of the clock driver. The reset controller needs to be selected from the machine as Ux500 has traditionally selected its mandatory subsystem prerequisites from there. Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20210921184803.1757916-2-linus.walleij@linaro.org Acked-by: Ulf Hansson <ulf.hansson@linaro.org> [sboyd@kernel.org: Dropped allocation error message] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
49 lines
1.0 KiB
Plaintext
49 lines
1.0 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0
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menuconfig ARCH_U8500
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bool "ST-Ericsson U8500 Series"
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depends on ARCH_MULTI_V7 && MMU
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select AB8500_CORE
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select ABX500_CORE
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select ARM_AMBA
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select ARM_ERRATA_754322
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select ARM_ERRATA_764369 if SMP
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select ARM_GIC
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select CACHE_L2X0
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select CLKSRC_DBX500_PRCMU
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select CLKSRC_NOMADIK_MTU
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select GPIOLIB
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select HAVE_ARM_SCU if SMP
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select HAVE_ARM_TWD if SMP
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select I2C
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select I2C_NOMADIK
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select MFD_DB8500_PRCMU
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select PINCTRL
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select PINCTRL_AB8500
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select PINCTRL_AB8505
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select PINCTRL_ABX500
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select PINCTRL_DB8500
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select PINCTRL_NOMADIK
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select PL310_ERRATA_753970 if CACHE_L2X0
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select PM_GENERIC_DOMAINS if PM
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select REGULATOR
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select REGULATOR_DB8500_PRCMU
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select REGULATOR_FIXED_VOLTAGE
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select SOC_BUS
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select RESET_CONTROLLER
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help
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Support for ST-Ericsson's Ux500 architecture
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if ARCH_U8500
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config UX500_SOC_DB8500
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def_bool y
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config UX500_DEBUG_UART
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int "Ux500 UART to use for low-level debug"
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default 2
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help
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Choose the UART on which kernel low-level debug messages should be
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output.
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endif
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