linux/arch/arm/mach-ux500/Kconfig
Linus Walleij b14cbdfd46 clk: ux500: Add driver for the reset portions of PRCC
The Ux500 PRCC (peripheral reset and clock controller) can also
control reset of the IP blocks, not just clocks. As the PRCC is probed
as a clock controller and we have other platforms implementing combined
clock and reset controllers, follow this pattern and implement the PRCC
rest controller as part of the clock driver.

The reset controller needs to be selected from the machine as Ux500 has
traditionally selected its mandatory subsystem prerequisites from there.

Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20210921184803.1757916-2-linus.walleij@linaro.org
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
[sboyd@kernel.org: Dropped allocation error message]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-26 18:06:05 -07:00

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# SPDX-License-Identifier: GPL-2.0
menuconfig ARCH_U8500
bool "ST-Ericsson U8500 Series"
depends on ARCH_MULTI_V7 && MMU
select AB8500_CORE
select ABX500_CORE
select ARM_AMBA
select ARM_ERRATA_754322
select ARM_ERRATA_764369 if SMP
select ARM_GIC
select CACHE_L2X0
select CLKSRC_DBX500_PRCMU
select CLKSRC_NOMADIK_MTU
select GPIOLIB
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select I2C
select I2C_NOMADIK
select MFD_DB8500_PRCMU
select PINCTRL
select PINCTRL_AB8500
select PINCTRL_AB8505
select PINCTRL_ABX500
select PINCTRL_DB8500
select PINCTRL_NOMADIK
select PL310_ERRATA_753970 if CACHE_L2X0
select PM_GENERIC_DOMAINS if PM
select REGULATOR
select REGULATOR_DB8500_PRCMU
select REGULATOR_FIXED_VOLTAGE
select SOC_BUS
select RESET_CONTROLLER
help
Support for ST-Ericsson's Ux500 architecture
if ARCH_U8500
config UX500_SOC_DB8500
def_bool y
config UX500_DEBUG_UART
int "Ux500 UART to use for low-level debug"
default 2
help
Choose the UART on which kernel low-level debug messages should be
output.
endif